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74VHC174TTR PDF预览

74VHC174TTR

更新时间: 2024-02-10 13:45:18
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
14页 316K
描述
HEX D-TYPE FLIP FLOP WITH CLEAR

74VHC174TTR 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-16针数:16
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.82Is Samacsys:N
系列:AHC/VHCJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:80000000 Hz最大I(ol):0.008 A
位数:6功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:10.5 ns传播延迟(tpd):16.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:110 MHzBase Number Matches:1

74VHC174TTR 数据手册

 浏览型号74VHC174TTR的Datasheet PDF文件第2页浏览型号74VHC174TTR的Datasheet PDF文件第3页浏览型号74VHC174TTR的Datasheet PDF文件第4页浏览型号74VHC174TTR的Datasheet PDF文件第5页浏览型号74VHC174TTR的Datasheet PDF文件第6页浏览型号74VHC174TTR的Datasheet PDF文件第7页 
74VHC174  
HEX D-TYPE FLIP FLOP WITH CLEAR  
HIGH SPEED:  
= 175MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4 µA (MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
SOP  
TSSOP  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
BALANCED PROPAGATION DELAYS:  
OH  
OL  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 174  
SOP  
74VHC174MTR  
74VHC174TTR  
V
CC  
TSSOP  
IMPROVED LATCH-UP IMMUNITY  
When the CLEAR input is held low, the Q outputs  
are held low independently of the other inputs.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
LOW NOISE: V  
= 0.8V (MAX.)  
OLP  
DESCRIPTION  
The 74VHC174 is an advanced high-speed  
CMOS HEX D-TYPE FLIP FLOP WITH CLEAR  
fabricated with sub-micron silicon gate and  
2
double-layer metal wiring C MOS technology.  
Information signals applied to D inputs are  
transferred to the Q outputs on the positive going  
edge of the clock pulse.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/14  
November 2004  

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