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74VHC14M PDF预览

74VHC14M

更新时间: 2024-11-15 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 224K
描述
HEX SCHMITT INVERTER

74VHC14M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.04
系列:AHC/VHCJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:INVERTER
最大I(ol):0.008 A湿度敏感等级:1
功能数量:6输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:2/5.5 VProp。Delay @ Nom-Sup:12 ns
传播延迟(tpd):18.5 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:1.75 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74VHC14M 数据手册

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74VHC14  
HEX SCHMITT INVERTER  
HIGH SPEED: t = 5.5ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 2 µA (MAX.) at T =25°C  
CC  
A
TYPICAL HYSTERESIS: V = 1V  
h
at V = 4.5V  
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 8 mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
T & R  
V
CC  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 14  
SOP  
74VHC14MTR  
74VHC14TTR  
TSSOP  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V  
= 0.8V (MAX.)  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
OLP  
Pin configuration and function are the same as  
those of the 74VHC04 but the 74VHC14 has  
hysteresis.  
This together with its schmitt trigger function  
allows it to be used on line receivers with slow  
rise/fall input signals.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHC14 is an advanced high-speed CMOS  
HEX SCHMITT INVERTER fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
The internal circuit is composed of 3 stages  
including buffer output, which enables high noise  
immunity and stable output.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 6  
1/11  
November 2004  

74VHC14M 替代型号

型号 品牌 替代类型 描述 数据表
SN74LV14ANSR TI

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