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74VHC125TTR PDF预览

74VHC125TTR

更新时间: 2024-11-24 04:48:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
12页 243K
描述
QUAD BUS BUFFERS (3-STATE)

74VHC125TTR 数据手册

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74VHC125  
QUAD BUS BUFFERS (3-STATE)  
HIGH SPEED: t = 3.8ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOP  
TSSOP  
|I | = I = 8mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
Table 1: Order Codes  
PACKAGE  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
T & R  
V
CC  
SOP  
74VHC125MTR  
74VHC125TTR  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 125  
TSSOP  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V  
= 0.8V (MAX.)  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
OLP  
DESCRIPTION  
The 74VHC125 is an advanced high-speed  
CMOS QUAD BUS BUFFERS fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
The device requires the 3-STATE control input G  
to be set high to place the output in to the high  
impedance state.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 7  
1/12  
November 2004  

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