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74VHC125N PDF预览

74VHC125N

更新时间: 2024-11-03 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 105K
描述
Quad Buffer with 3-STATE Outputs

74VHC125N 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP14,.3
针数:14Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.14
Is Samacsys:N控制类型:ENABLE LOW
系列:AHC/VHCJESD-30 代码:R-PDIP-T14
长度:19.18 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP14,.3封装形状:RECTANGULAR
封装形式:IN-LINE包装方法:RAIL
峰值回流温度(摄氏度):NOT SPECIFIED电源:2/5.5 V
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:5.08 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7.62 mm
Base Number Matches:1

74VHC125N 数据手册

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August 1993  
Revised February 2005  
74VHC125  
Quad Buffer with 3-STATE Outputs  
General Description  
Features  
The VHC125 contains four independent non-inverting buff-  
ers with 3-STATE outputs. It is an advanced high-speed  
CMOS device fabricated with silicon gate CMOS technol-  
ogy and achieves the high-speed operation similar to  
equivalent Bipolar Schottky TTL while maintaining the  
CMOS low power dissipation.  
High Speed: tPD 3.8 ns (typ) at VCC 5V  
Lower power dissipation: ICC A (max) at TA 25 C  
4
High noise immunity: VNIH VNIL 28% VCC (min)  
Power down protection is provided on all inputs  
Low noise: VOLP 0.8V (max)  
An input protection circuit insures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
Pin and function compatible with 74HC125  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74VHC125M  
M14A  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74VHC125MX_NL  
(Note 1)  
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
74VHC125SJ  
M14D  
MTC14  
MTC14  
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74VHC125MTC  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74VHC125MTCX_NL  
(Note 1)  
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74VHC125N  
N14A  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDED J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
© 2005 Fairchild Semiconductor Corporation  
DS011632  
www.fairchildsemi.com  

74VHC125N 替代型号

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