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74VHC125M PDF预览

74VHC125M

更新时间: 2024-11-03 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管PC
页数 文件大小 规格书
8页 64K
描述
QUAD BUS BUFFERS 3-STATE

74VHC125M 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.06
Is Samacsys:N控制类型:ENABLE LOW
系列:AHC/VHCJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TUBE
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):13 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mmBase Number Matches:1

74VHC125M 数据手册

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74VHC125  
QUAD BUS BUFFERS (3-STATE)  
PRELIMINARY DATA  
HIGH SPEED:tPD =3.8ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
CC =4 µA (MAX.) at TA =25 oC  
I
HIGH NOISEIMMUNITY:  
M
T
VNIH = VNIL =28% VCC (MIN.)  
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHC125M  
74VHC125T  
This device requires the 3-STATE control input G  
to be set high to place the output into the high  
impedance state.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES125  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2kV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHC125 is an advanced high-speed  
CMOS QUAD BUS BUFFERS fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
June 1999  

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