August 1993
Revised February 2005
74VHC125
Quad Buffer with 3-STATE Outputs
General Description
Features
The VHC125 contains four independent non-inverting buff-
ers with 3-STATE outputs. It is an advanced high-speed
CMOS device fabricated with silicon gate CMOS technol-
ogy and achieves the high-speed operation similar to
equivalent Bipolar Schottky TTL while maintaining the
CMOS low power dissipation.
■ High Speed: tPD 3.8 ns (typ) at VCC 5V
■ Lower power dissipation: ICC A (max) at TA 25 C
4
■ High noise immunity: VNIH VNIL 28% VCC (min)
■ Power down protection is provided on all inputs
■ Low noise: VOLP 0.8V (max)
An input protection circuit insures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery backup. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
■ Pin and function compatible with 74HC125
Ordering Code:
Package
Order Number
Package Description
Number
74VHC125M
M14A
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC125MX_NL
(Note 1)
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74VHC125SJ
M14D
MTC14
MTC14
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC125MTC
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC125MTCX_NL
(Note 1)
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74VHC125N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDED J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
© 2005 Fairchild Semiconductor Corporation
DS011632
www.fairchildsemi.com