Datasheet > 逻辑 > 栅极> 74VHC02SJX_NL

74VHC02SJX_NL

更新时间： 2024-11-16 13:04:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
7页	101K
描述
NOR Gate, CMOS, PDSO14,

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中文翻译

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技术参数
数据手册

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74VHC02SJX_NL 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
Reach Compliance Code：	compliant	风险等级：	5.84
Is Samacsys：	N	JESD-30 代码：	R-PDSO-G14
负载电容（CL）：	50 pF	逻辑集成电路类型：	NOR GATE
最大I（ol）：	0.008 A	端子数量：	14
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOP
封装等效代码：	SOP14,.3	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	包装方法：	TAPE AND REEL
电源：	2/5.5 V	Prop。Delay @ Nom-Sup：	8.5 ns
认证状态：	Not Qualified	施密特触发器：	NO
子类别：	Gates	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	Base Number Matches：	1

74VHC02SJX_NL 数据手册

November 1992

Revised February 2005

74VHC02

Quad 2-Input NOR Gate

General Description

Features

The VHC02 is an advanced high-speed CMOS 2-Input

NOR Gate fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The internal circuit is composed of 3

stages, including buffer output, which provide high noise

immunity and stable output. An input protection circuit

insures that 0V to 7V can be applied to the input pins with-

out regard to the supply voltage. This device can be used

to interface 5V to 3V systems and two supply systems such

as battery backup. This circuit prevents device destruction

due to mismatched supply and input voltages.

■ High Speed: t_PD3.6 ns (typ) at V_CC5V

■ Low power dissipation: I_CCA (max) at T_A25 C

■ High noise immunity: V_NIHV_NIL28% V_CC(min)

■ Power down protection is provided on all inputs

■ Low noise: V_OLP0.8V (max)

■ Pin and function compatible with 74HC02

Ordering Code:

Package

Order Number

Package Description

Number

74VHC02M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC02MX_NL

(Note 1)

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC02SJ

M14D

MTC14

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC02MTC

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC02MTCX_NL

(Note 1)

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74VHC02N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Logic Symbol

Connection Diagram

IEEE/IEC

Truth Table

Pin Descriptions

Pin Names

Description

Inputs

Outputs

A_n, B_n

O_n

DS011515

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

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与74VHC02SJX_NL相关器件

型号	品牌	获取价格	描述	数据表
74VHC02T	STMICROELECTRONICS	获取价格	QUAD 2-INPUT NOR GATE
74VHC02TTR	STMICROELECTRONICS	获取价格	QUAD 2-INPUT NOR GATE
74VHC02TTR	FAIRCHILD	获取价格	QUAD 2-INPUT NOR GATE
74VHC03	STMICROELECTRONICS	获取价格	QUAD 2-INPUT OPEN DRAIN NAND GATE
74VHC03_04	STMICROELECTRONICS	获取价格	QUAD 2-INPUT OPEN DRAIN NAND GATE
74VHC03FT	TOSHIBA	获取价格	Quad 2-Input/NAND, TSSOP14B
74VHC03M	STMICROELECTRONICS	获取价格	QUAD 2-INPUT OPEN DRAIN NAND GATE
74VHC03MTR	STMICROELECTRONICS	获取价格	QUAD 2-INPUT OPEN DRAIN NAND GATE
74VHC03T	STMICROELECTRONICS	获取价格	QUAD 2-INPUT OPEN DRAIN NAND GATE
74VHC03TTR	STMICROELECTRONICS	获取价格	QUAD 2-INPUT OPEN DRAIN NAND GATE

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