Datasheet > 逻辑 > 栅极> 74VHC02NX

74VHC02NX

更新时间： 2024-11-15 22:37:03

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		栅
页数	文件大小	规格书
7页	101K
描述
Quad 2-Input NOR Gate

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

74VHC02NX 数据手册

November 1992

Revised February 2005

74VHC02

Quad 2-Input NOR Gate

General Description

Features

The VHC02 is an advanced high-speed CMOS 2-Input

NOR Gate fabricated with silicon gate CMOS technology. It

achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The internal circuit is composed of 3

stages, including buffer output, which provide high noise

immunity and stable output. An input protection circuit

insures that 0V to 7V can be applied to the input pins with-

out regard to the supply voltage. This device can be used

to interface 5V to 3V systems and two supply systems such

as battery backup. This circuit prevents device destruction

due to mismatched supply and input voltages.

■ High Speed: t_PD3.6 ns (typ) at V_CC5V

■ Low power dissipation: I_CCA (max) at T_A25 C

■ High noise immunity: V_NIHV_NIL28% V_CC(min)

■ Power down protection is provided on all inputs

■ Low noise: V_OLP0.8V (max)

■ Pin and function compatible with 74HC02

Ordering Code:

Package

Order Number

Package Description

Number

74VHC02M

M14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC02MX_NL

(Note 1)

Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC02SJ

M14D

MTC14

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC02MTC

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC02MTCX_NL

(Note 1)

Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74VHC02N

N14A

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.

Logic Symbol

Connection Diagram

IEEE/IEC

Truth Table

Pin Descriptions

Pin Names

Description

Inputs

Outputs

A_n, B_n

O_n

DS011515

www.fairchildsemi.com

12 3 4 5 6 7

中文翻译

下载PDF

与74VHC02NX相关器件

型号	品牌	获取价格	描述	数据表
74VHC02PW	NXP	获取价格	Quad 2-input NOR gate
74VHC02PW	NEXPERIA	获取价格	Quad 2-input NOR gateProduction
74VHC02PW-Q100	NXP	获取价格	IC AHC/VHC/H/U/V SERIES, QUAD 2-INPUT NOR GATE, PDSO14, 4.40 MM, PLASTIC, MO-153, SOT402-1
74VHC02PW-Q100	NEXPERIA	获取价格	Quad 2-input NOR gate
74VHC02PW-Q100J	NXP	获取价格	74VHC(T)02-Q100 - Quad 2-input NOR gate TSSOP 14-Pin
74VHC02-Q100	NEXPERIA	获取价格	Quad 2-input NOR gate
74VHC02SJ	FAIRCHILD	获取价格	Quad 2-Input NOR Gate
74VHC02SJX	FAIRCHILD	获取价格	Quad 2-Input NOR Gate
74VHC02SJX_NL	FAIRCHILD	获取价格	NOR Gate, CMOS, PDSO14,
74VHC02T	STMICROELECTRONICS	获取价格	QUAD 2-INPUT NOR GATE