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74VCXH16374TTR PDF预览

74VCXH16374TTR

更新时间: 2024-11-08 22:49:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件输入元件
页数 文件大小 规格书
12页 288K
描述
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)WITH 3.6V TOLERANT INPUTS AND OUTPUTS

74VCXH16374TTR 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-48
针数:48Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.33
Is Samacsys:N系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G48JESD-609代码:e4
长度:12.5 mm负载电容(CL):30 pF
逻辑集成电路类型:BUS DRIVER最大频率@ Nom-Sup:235000000 Hz
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:2
端口数量:2端子数量:48
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:3.5 ns传播延迟(tpd):4.7 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:6.1 mm
Base Number Matches:1

74VCXH16374TTR 数据手册

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74VCXH16374  
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)  
WITH 3.6V TOLERANT INPUTS AND OUTPUTS  
3.6V TOLERANT INPUTS AND OUTPUTS  
HIGH SPEED :  
t
t
= 3.0 ns (MAX.) at V = 3.0 to 3.6V  
PD  
CC  
= 3.9 ns (MAX.) at V = 2.3 to 2.7V  
PD  
CC  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
TSSOP  
TUBE  
|I | = I = 24mA (MIN) at V = 3.0V  
OH  
OL  
CC  
|I | = I = 18mA (MIN) at V = 2.3V  
OH  
OL  
CC  
OPERATING VOLTAGE RANGE:  
(OPR) = 2.3V to 3.6V  
ORDER CODES  
PACKAGE  
V
CC  
T & R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES H16374  
TSSOP  
74VCXH16374TTR  
BUS HOLD PROVIDED ON DATA INPUTS  
LATCH-UP PERFORMANCE EXCEEDS  
300mA (JESD 17)  
PIN CONNECTION  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
DESCRIPTION  
The 74VCXH16374 is a low voltage CMOS 16 BIT  
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS  
NON INVERTING fabricated with sub-micron  
2
silicon gate and five-layer metal wiring C MOS  
technology. It is ideal for low power and very high  
speed 2.3 to 3.6V applications; it can be interfaced  
to 3.6V signal environment for both inputs and  
outputs.  
These 16 bit D-TYPE flip-flops are controlled by  
two clock inputs (nCK) and two output enable  
inputs (nOE).  
On the positive transition of the (nCK), the nQ  
outputs will be set to the logic state that were  
setup at the nD inputs.  
While the (nOE) input is low, the 8 outputs (nQ)  
will be in a normal state (HIGH or LOW logic level)  
and while high level the outputs will be in a high  
impedance state.  
Any output control does not affect the internal  
operation of flip flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off.  
Bus hold on data inputs is provided in order to  
eliminate the need for external pull-up or  
pull-down resistor.  
February 2003  
1/12  

74VCXH16374TTR 替代型号

型号 品牌 替代类型 描述 数据表
SN74ALVCH16374DGGR TI

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