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74VCXH16374 PDF预览

74VCXH16374

更新时间: 2024-09-16 04:48:03
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安森美 - ONSEMI 触发器
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11页 247K
描述
Low−Voltage 1.8/2.5/3.3V 16-Bit D−Type Flip−Flop With 3.6 V-Tolerant Inputs and Outputs (3-State, Non-Inverting)

74VCXH16374 数据手册

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74VCXH16374  
Low−Voltage 1.8/2.5/3.3V  
16−Bit D−Type Flip−Flop  
With 3.6 VTolerant Inputs and Outputs  
(3State, NonInverting)  
The 74VCXH16374 is an advanced performance, noninverting  
16bit Dtype flipflop. It is designed for very highspeed, very  
lowpower operation in 1.8 V, 2.5 V or 3.3 V systems. The VCXH16374  
is byte controlled, with each byte functioning identically, but  
independently. Each byte has separate Output Enable and Clock Pulse  
inputs. These control pins can be tied together for full 16bit operation.  
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6V.  
The 74VCXH16374 consists of 16 edgetriggered flipflops with  
individual Dtype inputs and 3.6 Vtolerant 3state outputs. The  
clocks (CPn) and Output Enables (OEn) are common to all flipflops  
within the respective byte. The flipflops will store the state of  
individual D inputs that meet the setup and hold time requirements on  
the LOWtoHIGH Clock (CP) transition. With the OE LOW, the  
contents of the flipflops are available at the outputs. When the OE is  
HIGH, the outputs go to the high impedance state. The OE input level  
does not affect the operation of the flipflops. The data inputs include  
active bushold circuitry, eliminating the need for external pullup  
resistors to hold unused or floating inputs at a valid logic state.  
http://onsemi.com  
MARKING DIAGRAM  
48  
48  
VCXH16374  
AWLYYWW  
1
TSSOP48  
DT SUFFIX  
CASE 1201  
1
A
= Assembly Location  
= Wafer Lot  
= Year  
WL  
YY  
WW  
= Work Week  
PIN NAMES  
Pins  
Function  
Features  
OEn  
CPn  
D0D15  
O0O15  
Output Enable Inputs  
Clock Pulse Inputs  
Inputs  
Designed for Low Voltage Operation: V = 1.65 V 3.6 V  
3.6 V Tolerant Inputs and Outputs  
High Speed Operation: 3.0 ns max for 3.0 V to 3.6V  
CC  
Outputs  
3.9 ns max for 2.3 V to 2.7V  
7.8 ns max for 1.65 V to 1.95V  
Static Drive: ±24 mA Drive at 3.0 V  
±18 mA Drive at 2.3 V  
±6 mA Drive at 1.65 V  
Supports Live Insertion and Withdrawal  
ORDERING INFORMATION  
Device  
Package  
Shipping  
39 / Rail  
74VCXH16374DT  
TSSOP  
(PbFree)  
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid  
74VCXH16374DTR  
TSSOP  
(PbFree)  
2500 / Reel  
Logic State  
I  
Specification Guarantees High Impedance When V = 0 V*  
CC  
OFF  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Near Zero Static Supply Current in All Three Logic States (20 mA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds ±250 mA @ 125°C  
ESD Performance: Human Body Model >2000 V  
Machine Model >200 V  
All Devices in Package TSSOP are Inherently PbFree**  
*To ensure the outputs activate in the 3state condition, the output enable pins  
should be connected to V through a pullup resistor. The value of the resistor  
CC  
is determined by the current sinking capability of the output connected to the  
OE pin.  
**For additional information on our PbFree strategy and soldering details,  
please download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 Rev. 5  
74VCXH16374/D  

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