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74VCXH16373GX PDF预览

74VCXH16373GX

更新时间: 2024-11-05 23:24:35
品牌 Logo 应用领域
其他 - ETC 锁存器逻辑集成电路驱动
页数 文件大小 规格书
9页 107K
描述
8-Bit D-Type Latch

74VCXH16373GX 数据手册

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January 2000  
Revised August 2001  
74VCXH16373  
Low Voltage 16-Bit Transparent Latch with Bushold  
General Description  
Features  
The VCXH16373 contains sixteen non-inverting latches  
with 3-STATE outputs and is intended for bus oriented  
applications. The device is byte controlled. The flip-flops  
appear to be transparent to the data when the Latch  
Enable (LE) is HIGH. When LE is LOW, the data that meets  
the setup time is latched. Data appears on the bus when  
the Output Enable (OE) is LOW. When OE is HIGH, the  
outputs are in a high impedance state.  
1.65V–3.6V VCC supply operation  
3.6V tolerant control inputs and outputs  
Bushold on data inputs eliminates the need for external  
pull-up/pull-down resistors  
tPD (In to On)  
3.0 ns max for 3.0V to 3.6V VCC  
3.4 ns max for 2.3V to 2.7V VCC  
6.8 ns max for 1.65V to 1.95V VCC  
The VCXH16373 data inputs include active bushold cir-  
cuitry, eliminating the need for external pull-up resistors to  
hold unused or floating data inputs at a valid logic level.  
Static Drive (IOH/IOL  
)
The 74VCXH16373 is designed for low voltage (1.65V to  
3.6V) VCC applications with output compatibility up to 3.6V.  
±24 mA @ 3.0V VCC  
±18 mA @ 2.3V VCC  
±6 mA @ 1.65V VCC  
The 74VCXH16373 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA) (Preliminary)  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74VCXH16373GX  
(Note 1)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[TAPE and REEL]  
74VCXH16373MTD  
(Note 2)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
Note 1: BGA package available in Tape and Reel only.  
Note 2: Devices also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Logic Symbol  
© 2001 Fairchild Semiconductor Corporation  
DS500229  
www.fairchildsemi.com  

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