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74VCXH16373DTRG PDF预览

74VCXH16373DTRG

更新时间： 2024-11-06 04:48:03
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 247K
描述
Low−Voltage 1.8/2.5/3.3 V 16−Bit Transparent Latch

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74VCXH16373DTRG 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：LEAD FREE, TSSOP-48
针数：48Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.2
Is Samacsys：N系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G48JESD-609代码：e1
长度：12.5 mm负载电容（CL）：30 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：3 ns传播延迟（tpd）：7.8 ns
认证状态：Not Qualified座面最大高度：1.1 mm
子类别：FF/Latches最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN SILVER COPPER
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmBase Number Matches：1

74VCXH16373DTRG 数据手册

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74VCXH16373  
Low−Voltage 1.8/2.5/3.3 V  
16−Bit Transparent Latch  
With 3.6 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
The 74VCXH16373 is an advanced performance, non−inverting  
16−bit transparent latch. It is designed for very high−speed, very  
low−power operation in 1.8 V, 2.5 V or 3.3 V systems. The  
VCXH16373 is byte controlled, with each byte functioning  
identically, but independently. Each byte has separate Output Enable  
and Latch Enable inputs. These control pins can be tied together for  
full 16−bit operation.  
http://onsemi.com  
TSSOP−48  
48  
DT SUFFIX  
CASE 1201  
1
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V.  
The 74VCXH16373 contains 16 D−type latches with 3−state  
3.6 V−tolerant outputs. When the Latch Enable (LEn) inputs are  
HIGH, data on the Dn inputs enters the latches. In this condition, the  
latches are transparent, (a latch output will change state each time its D  
input changes). When LE is LOW, the latch stores the information that  
was present on the D inputs a setup time preceding the  
HIGH−to−LOW transition of LE. The 3−state outputs are controlled  
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are  
enabled. When OE is HIGH, the standard outputs are in the high  
impedance state, but this does not interfere with new data entering into  
the latches. The data inputs include active bushold circuitry,  
eliminating the need for external pullup resistors to hold unused or  
floating inputs at a valid logic state.  
MARKING DIAGRAM  
48  
VCXH16373  
AWLYYWW  
1
A
WL  
YY  
= Assembly Location  
= Wafer Lot  
= Year  
WW  
= Work Week  
Features  
PIN NAMES  
• Designed for Low Voltage Operation: V = 1.65 V − 3.6 V  
CC  
Pins  
Function  
• 3.6 V Tolerant Inputs and Outputs  
• High Speed Operation: 3.0 ns max for 3.0 V to 3.6 V  
OEn  
LEn  
D0−D15  
O0−O15  
Output Enable Inputs  
Latch Enable Inputs  
Inputs  
3.9 ns max for 2.3 V to 2.7 V  
6.8 ns max for 1.65 V to 1.95 V  
Outputs  
• Static Drive: ±24 mA Drive at 3.0 V  
±18 mA Drive at 2.3 V  
±6 mA Drive at 1.65 V  
• Supports Live Insertion and Withdrawal  
ORDERING INFORMATION  
†
Device  
Package  
Shipping  
39 / Rail  
74VCXH16373DT  
74VCXH16373DTR  
TSSOP  
• Includes Active Bushold to Hold Unused or Floating Inputs at  
a Valid Logic State  
TSSOP 2500/Tape & Reel  
• I  
Specification Guarantees High Impedance When V = 0 V*  
CC  
OFF  
74VCXH16373DTRG TSSOP 2500/Tape & Reel  
• Near Zero Static Supply Current in All Three Logic States (20 mA)  
(Pb−Free)  
Substantially Reduces System Power Requirements  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
• Latchup Performance Exceeds ±250 mA @ 125°C  
• ESD Performance: Human Body Model >2000 V  
Machine Model >200 V  
• Pb−Free Package is Available**  
**For additional information on our Pb−Free strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
*To ensure the outputs activate in the 3−state condition,  
the output enable pins should be connected to V through a  
CC  
pull−up resistor. The value of the resistor is determined by the  
current sinking capability of the output connected to the OE pin.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 − Rev. 6  
74VCXH16373/D  
1234567...11

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 		LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)WITH 3.6V TOLERANT INPUTS AND OUTPUTS
74VCXH16374 ONSEMI

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 		Low−Voltage 1.8/2.5/3.3V 16-Bit D−Type Flip−Flop With 3.6 V-Tolerant Inp
74VCXH16374 FAIRCHILD

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 		Low Voltage 16-Bit D-Type Flip-Flop with Bushold
74VCXH16374/D ETC

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 		Low-Voltage 1.8/2.5/3.3V 16-Bit D-Type Flip-Flop
74VCXH16374DT ONSEMI

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 		Low−Voltage 1.8/2.5/3.3V 16-Bit D−Type Flip−Flop With 3.6 V-Tolerant Inp

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