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74VCXH16373/D PDF预览

74VCXH16373/D

更新时间: 2024-09-15 23:24:35
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描述
Low-Voltage 1.8/2.5/3.3V 16-Bit Transceiver

74VCXH16373/D 数据手册

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74VCXH16373  
Low-Voltage 1.8/2.5/3.3V  
16-Bit Transparent Latch  
With 3.6V–Tolerant Inputs and Outputs  
(3–State, Non–Inverting)  
The 74VCXH16373 is an advanced performance, non–inverting  
16–bit transparent latch. It is designed for very high–speed, very  
low–power operation in 1.8V, 2.5V or 3.3V systems. The  
VCXH16373 is byte controlled, with each byte functioning  
identically, but independently. Each byte has separate Output Enable  
and Latch Enable inputs. These control pins can be tied together for  
full 16–bit operation.  
When operating at 2.5V (or 1.8V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3V busses. It is guaranteed to be over–voltage tolerant to 3.6V.  
The 74VCXH16373 contains 16 D–type latches with 3–state  
3.6V–tolerant outputs. When the Latch Enable (LEn) inputs are  
HIGH, data on the Dn inputs enters the latches. In this condition, the  
latches are transparent, (a latch output will change state each time its D  
input changes). When LE is LOW, the latch stores the information that  
was present on the D inputs a setup time preceding the  
HIGH–to–LOW transition of LE. The 3–state outputs are controlled  
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are  
enabled. When OE is HIGH, the standard outputs are in the high  
impedance state, but this does not interfere with new data entering into  
the latches. The data inputs include active bushold circuitry,  
eliminating the need for external pull–up resistors to hold unused or  
floating inputs at a valid logic state.  
http://onsemi.com  
MARKING DIAGRAM  
48  
48  
74VCXH16373DT  
AWLYYWW  
1
TSSOP–48  
DT SUFFIX  
CASE 1201  
1
= Assembly Location  
A
WL = Wafer Lot  
YY = Year  
WW = Work Week  
PIN NAMES  
Pins  
Function  
OEn  
LEn  
D0–D15  
O0–O15  
Output Enable Inputs  
Latch Enable Inputs  
Inputs  
Outputs  
Designed for Low Voltage Operation: V = 1.65–3.6V  
CC  
3.6V Tolerant Inputs and Outputs  
High Speed Operation: 3.0ns max for 3.0 to 3.6V  
3.9ns max for 2.3 to 2.7V  
ORDERING INFORMATION  
Device  
Package  
TSSOP  
TSSOP  
Shipping  
39 / Rail  
6.8ns max for 1.65 to 1.95V  
74VCXH16373DT  
74VCXH16373DTR  
Static Drive: ±24mA Drive at 3.0V  
±18mA Drive at 2.3V  
2500 / Reel  
±6mA Drive at 1.65V  
Supports Live Insertion and Withdrawal  
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid  
Logic State  
I  
Specification Guarantees High Impedance When V = 0V  
CC  
OFF  
Near Zero Static Supply Current in All Three Logic States (20µA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds ±250mA @ 125°C  
ESD Performance: Human Body Model >2000V; Machine Model  
>200V  
†NOTE: To ensure the outputs activate in the 3–state condition, the output  
enable pins should be connected to V  
through a pull–up resistor. The  
CC  
value of the resistor is determined by the current sinking capability of the  
output connected to the OE pin.  
Semiconductor Components Industries, LLC, 2001  
1
Publication Order Number:  
January, 2001 – Rev. 1  
74VCXH16373/D  

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