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74VCXH16373 PDF预览

74VCXH16373

更新时间: 2024-09-16 04:48:03
品牌 Logo 应用领域
安森美 - ONSEMI 锁存器
页数 文件大小 规格书
11页 247K
描述
Low−Voltage 1.8/2.5/3.3 V 16−Bit Transparent Latch

74VCXH16373 数据手册

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74VCXH16373  
Low−Voltage 1.8/2.5/3.3 V  
16−Bit Transparent Latch  
With 3.6 VTolerant Inputs and Outputs  
(3State, NonInverting)  
The 74VCXH16373 is an advanced performance, noninverting  
16bit transparent latch. It is designed for very highspeed, very  
lowpower operation in 1.8 V, 2.5 V or 3.3 V systems. The  
VCXH16373 is byte controlled, with each byte functioning  
identically, but independently. Each byte has separate Output Enable  
and Latch Enable inputs. These control pins can be tied together for  
full 16bit operation.  
http://onsemi.com  
TSSOP48  
48  
DT SUFFIX  
CASE 1201  
1
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V.  
The 74VCXH16373 contains 16 Dtype latches with 3state  
3.6 Vtolerant outputs. When the Latch Enable (LEn) inputs are  
HIGH, data on the Dn inputs enters the latches. In this condition, the  
latches are transparent, (a latch output will change state each time its D  
input changes). When LE is LOW, the latch stores the information that  
was present on the D inputs a setup time preceding the  
HIGHtoLOW transition of LE. The 3state outputs are controlled  
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are  
enabled. When OE is HIGH, the standard outputs are in the high  
impedance state, but this does not interfere with new data entering into  
the latches. The data inputs include active bushold circuitry,  
eliminating the need for external pullup resistors to hold unused or  
floating inputs at a valid logic state.  
MARKING DIAGRAM  
48  
VCXH16373  
AWLYYWW  
1
A
WL  
YY  
= Assembly Location  
= Wafer Lot  
= Year  
WW  
= Work Week  
Features  
PIN NAMES  
Designed for Low Voltage Operation: V = 1.65 V 3.6 V  
CC  
Pins  
Function  
3.6 V Tolerant Inputs and Outputs  
High Speed Operation: 3.0 ns max for 3.0 V to 3.6 V  
OEn  
LEn  
D0D15  
O0O15  
Output Enable Inputs  
Latch Enable Inputs  
Inputs  
3.9 ns max for 2.3 V to 2.7 V  
6.8 ns max for 1.65 V to 1.95 V  
Outputs  
Static Drive: ±24 mA Drive at 3.0 V  
±18 mA Drive at 2.3 V  
±6 mA Drive at 1.65 V  
Supports Live Insertion and Withdrawal  
ORDERING INFORMATION  
Device  
Package  
Shipping  
39 / Rail  
74VCXH16373DT  
74VCXH16373DTR  
TSSOP  
Includes Active Bushold to Hold Unused or Floating Inputs at  
a Valid Logic State  
TSSOP 2500/Tape & Reel  
I  
Specification Guarantees High Impedance When V = 0 V*  
CC  
OFF  
74VCXH16373DTRG TSSOP 2500/Tape & Reel  
Near Zero Static Supply Current in All Three Logic States (20 mA)  
(PbFree)  
Substantially Reduces System Power Requirements  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Latchup Performance Exceeds ±250 mA @ 125°C  
ESD Performance: Human Body Model >2000 V  
Machine Model >200 V  
PbFree Package is Available**  
**For additional information on our PbFree strategy  
and soldering details, please download the  
ON Semiconductor Soldering and Mounting  
Techniques Reference Manual, SOLDERRM/D.  
*To ensure the outputs activate in the 3state condition,  
the output enable pins should be connected to V through a  
CC  
pullup resistor. The value of the resistor is determined by the  
current sinking capability of the output connected to the OE pin.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 Rev. 6  
74VCXH16373/D  

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