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74VCXH16244DTR PDF预览

74VCXH16244DTR

更新时间: 2024-09-15 20:28:39
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
12页 88K
描述
ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, LEAD FREE, TSSOP-48

74VCXH16244DTR 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP48,.3,20
针数:48Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.7
Is Samacsys:N控制类型:ENABLE LOW
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G48
JESD-609代码:e0长度:12.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:4功能数量:4
端口数量:2端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP48,.3,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:3 ns传播延迟(tpd):6 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mmBase Number Matches:1

74VCXH16244DTR 数据手册

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74VCXH16244  
Low−Voltage 1.8/2.5/3.3V  
16−Bit Buffer  
With 3.6 V−Tolerant Inputs and Outputs  
(3−State, Non−Inverting)  
The 74VCXH16244 is an advanced performance, non−inverting  
16−bit buffer. It is designed for very high−speed, very low−power  
operation in 1.8 V, 2.5 V or 3.3 V systems.  
http://onsemi.com  
MARKING DIAGRAM  
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate  
voltages it may encounter on either inputs or outputs when interfacing  
to 3.3 V busses. It is guaranteed to be overvoltage tolerant to 3.6 V.  
The 74VCXH16244 is nibble controlled with each nibble  
functioning identically, but independently. The control pins may be  
tied together to obtain full 16−bit operation. The 3−state outputs are  
controlled by an Output Enable (OEn) input for each nibble. When  
OEn is LOW, the outputs are on. When OEn is HIGH, the outputs are  
in the high impedance state. The data inputs include active bushold  
circuitry, eliminating the need for external pullup resistors to hold  
unused or floating inputs at a valid logic state.  
48  
48  
VCXH16244  
AWLYYWW  
1
TSSOP−48  
DT SUFFIX  
CASE 1201  
1
A
= Assembly Location  
= Wafer Lot  
= Year  
WL  
YY  
WW  
Features  
= Work Week  
Designed for Low Voltage Operation: V = 1.65 V − 3.6 V  
CC  
3.6 V Tolerant Inputs and Outputs  
ORDERING INFORMATION  
High Speed Operation: 2.5 ns max for 3.0 V to 3.6 V  
3.0 ns max for 2.3 V to 2.7 V  
Device  
Package  
Shipping  
39 / Rail  
74VCXH16244DT  
TSSOP  
(Pb−Free)  
6.0 ns max for 1.65 V to 1.95 V  
Static Drive:  
±24 mA Drive at 3.0 V  
±18 mA Drive at 2.3 V  
±6 mA Drive at 1.65 V  
74VCXH16244DTR  
TSSOP  
(Pb−Free)  
2500 / Reel  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
Supports Live Insertion and Withdrawal  
Includes Active Bushold to Hold Unused or Floating Inputs at a Valid  
Logic State  
I  
Specification Guarantees High Impedance When V = 0 V*  
CC  
OFF  
Near Zero Static Supply Current in All Three Logic States (20 mA)  
Substantially Reduces System Power Requirements  
Latchup Performance Exceeds ±250 mA @ 125°C  
ESD Performance: Human Body Model >2000 V  
Machine Model >200 V  
All Devices in Package TSSOP are Inherently Pb−Free**  
*To ensure the outputs activate in the 3−state condition, the output enable pins  
should be connected to V through a pullup resistor. The value of the resistor  
CC  
is determined by the current sinking capability of the output connected to the  
OE pin.  
**For additional information on our Pb−Free strategy and soldering details,  
please download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
Semiconductor Components Industries, LLC, 2004  
1
Publication Order Number:  
November, 2004 − Rev. 4  
74VCXH16244/D  

74VCXH16244DTR 替代型号

型号 品牌 替代类型 描述 数据表
74ALVCH16244DGGRE4 TI

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