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74VCXH16240T PDF预览

74VCXH16240T

更新时间: 2024-11-09 14:37:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 73K
描述
ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, INVERTED OUTPUT, PDSO48, TSSOP-48

74VCXH16240T 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-48
针数:48Reach Compliance Code:not_compliant
风险等级:5.2Is Samacsys:N
控制类型:ENABLE LOW系列:ALVC/VCX/A
JESD-30 代码:R-PDSO-G48JESD-609代码:e0
长度:12.5 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:4
功能数量:4端口数量:2
端子数量:48最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:INVERTED封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP48,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:2.5 ns传播延迟(tpd):3.8 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.3 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:6.1 mmBase Number Matches:1

74VCXH16240T 数据手册

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74VCXH16240  
LOW VOLTAGE CMOS 16-BIT BUFFER (3-STATE INV.)  
WITH 3.6V TOLERANT INPUTS AND OUTPUTS  
PRELIMINARY DATA  
3.6VTOLERANT INPUTS ANDOUTPUTS  
HIGH SPEED:  
tPD =2.5 ns (MAX.)atVCC = 3.0 to3.6V  
tPD =3.0 ns (MAX.)atVCC = 2.3 to2.7V  
POWER-DOWN PROTECTIONON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
T
(TSSOP48 Package)  
|IOH| = IOL = 24 mA (MIN) at VCC = 3.0V  
|IOH| = IOL = 18 mA (MIN) at VCC = 2.3V  
OPERATING VOLTAGERANGE:  
ORDER CODES :  
74VCXH16240T  
V
CC (OPR)= 1.8V to 3.6V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES16240  
PIN CONNECTION  
BUS HOLD PROVIDED ON DATA INPUTS  
LATCH-UPPERFORMANCE EXCEEDS300mA  
ESDPERFORMANCE:  
HBM >2000V; MM > 200V  
DESCRIPTION  
The 74VCXH16240 is a low voltage CMOS  
16-BIT BUS BUFFER (INVERTED) fabricated  
with sub-micron silicon gate and five layer metal  
wiring C2MOS technology. It is ideal for low  
power and very high speed 2.3 to 3.6V  
applications; it can be interfaced to 3.6V signal  
enviroment for both inputs and outputs.  
Any nG control output governs four BUS  
BUFFERS. Output Enable input (nG) tied  
togethergives full 16-bit operation.  
When nG is LOW, the outputs are on. When nG  
is HIGH, the output are in high impedance state.  
This device is designed to be used with 3 state  
memory address drivers, etc. Bus hold on data  
inputs is provided in order to eliminate te need for  
external pull-up or pull-down resistor.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
1/9  
March 1999  

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