January 2000
Revised March 2000
74VCXH162373
Low Voltage 16-Bit Transparent Latch with Bushold
and 26Ω Series Resistors in Outputs
General Description
Features
■ 1.65V–3.6V VCC supply operation
The VCXH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
■ 3.6V tolerant control inputs and outputs
■ Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors
■ 26Ω series resistors in outputs
■ tPD (In to On)
3.3 ns max for 3.0V to 3.6V VCC
4.5 ns max for 2.3V to 2.7V VCC
9.0 ns max for 1.65V to 1.95V VCC
The VCXH162373 data inputs include active bushold cir-
cuitry, eliminating the need for external pull-up resistors to
hold unused or floating data inputs at a valid logic level.
The VCXH162373 is also designed with 26Ω series resis-
tors in the outputs. This design reduces line noise in appli-
cations such as memory address driver, clock drivers and
bus transceivers/transmitters.
■ Static Drive (IOH/IOL
)
±12 mA @ 3.0V VCC
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
The 74VCXH162373 is designed for low voltage (1.65V to
3.6V) VCC applications with output compatibility up to 3.6V.
■ Uses patented noise/EMI reduction circuitry
■ Latch-up performance exceeds 300 mA
■ ESD performance:
The 74VCXH162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Human body model > 2000V
Machine model > 200V
Ordering Code:
Package
Ordering Number
Number
Package Description
74VCXH162373MTD
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
MTD48
MTD48
74VCXH162373MTX
(Note 1)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
Pin Descriptions
Pin Names
Description
OEn
Output Enable Input (Active LOW)
Latch Enable Input
Bushold Inputs
LEn
I0–I15
O0–O15
Outputs
© 2000 Fairchild Semiconductor Corporation
DS500227
www.fairchildsemi.com