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74VCX32374G PDF预览

74VCX32374G

更新时间: 2024-09-15 22:45:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器触发器逻辑集成电路
页数 文件大小 规格书
9页 130K
描述
Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs

74VCX32374G 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:LFBGA, BGA96,6X16,32
针数:96Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.52
系列:ALVC/VCX/AJESD-30 代码:R-PBGA-B96
JESD-609代码:e0长度:13.5 mm
负载电容(CL):30 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:250000000 Hz最大I(ol):0.024 A
湿度敏感等级:3位数:8
功能数量:4端口数量:2
端子数量:96最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LFBGA封装等效代码:BGA96,6X16,32
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法:TRAY峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:3 ns
传播延迟(tpd):39 ns认证状态:Not Qualified
座面最大高度:1.4 mm子类别:FF/Latches
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:5.5 mmBase Number Matches:1

74VCX32374G 数据手册

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December 2000  
Revised November 2002  
74VCX32374  
Low Voltage 32-Bit D-Type Flip-Flops  
with 3.6V Tolerant Inputs and Outputs  
General Description  
Features  
1.2V to 3.6V VCC supply operation  
The VCX32374 contains thirty-two non-inverting D-type  
flip-flops with 3-STATE outputs and is intended for bus ori-  
ented applications. The device is byte controlled. A buff-  
ered clock (CP) and output enable (OE) are common to  
each byte and can be shorted together for full 32-bit opera-  
tion.  
3.6V tolerant inputs and outputs  
tPD  
3.0 ns max for 3.0V to 3.6V VCC  
Power-off high impedance inputs and outputs  
Supports live insertion and withdrawal (Note 1)  
The 74VCX32374 is designed for low voltage (1.2V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
Static Drive (IOH/IOL  
)
The 74VCX32374 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
±24 mA @ 3.0V VCC  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor; the minimum  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Descriptions  
74VCX32374G  
(Note 2)(Note 3)  
BGA96A  
96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
Note 2: Ordering code “G” indicates Trays.  
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
© 2002 Fairchild Semiconductor Corporation  
DS500402  
www.fairchildsemi.com  

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