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74VCX32373GX

更新时间： 2024-11-24 22:36:07

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线驱动器总线收发器锁存器逻辑集成电路
页数	文件大小	规格书
8页	213K
描述
Low Voltage 32-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs (Preliminary)

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技术参数
数据手册

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74VCX32373GX 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	5.50 MM, PLASTIC, MO-205, FBGA-96
针数：	96	Reach Compliance Code：	compliant
风险等级：	5.91	Is Samacsys：	N
系列：	ALVC/VCX/A	JESD-30 代码：	R-PBGA-B96
JESD-609代码：	e0	长度：	13.5 mm
负载电容（CL）：	30 pF	逻辑集成电路类型：	BUS DRIVER
最大I（ol）：	0.024 A	位数：	8
功能数量：	4	端口数量：	2
端子数量：	96	最高工作温度：	85 °C
最低工作温度：	-40 °C	输出特性：	3-STATE
输出极性：	TRUE	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFBGA	封装等效代码：	BGA96,6X16,32
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	电源：	3.3 V
Prop。Delay @ Nom-Sup：	3 ns	传播延迟（tpd）：	7.8 ns
认证状态：	Not Qualified	座面最大高度：	1.4 mm
子类别：	FF/Latches	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	1.65 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.5 mm	Base Number Matches：	1

74VCX32373GX 数据手册

Preliminary

February 2001

Revised August 2001

74VCX32373

Low Voltage 32-Bit Transparent Latch

with 3.6V Tolerant Inputs and Outputs (Preliminary)

General Description

Features

■ 1.65V–3.6V V_CCsupply operation

The VCX32373 contains thirty-two non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup time is latched. Data appears on the bus when the

Output Enable (OE) is LOW. When OE is HIGH, the out-

puts are in a high impedance state.

■ 3.6V tolerant inputs and outputs

■ t_PD(I_nto O_n)

3.0 ns max for 3.0V to 3.6V V_CC

3.4 ns max for 2.3V to 2.7V V_CC

6.8 ns max for 1.65V to 1.95V V_CC

■ Power-off high impedance inputs and outputs

■ Support live insertion and withdrawal (Note 1)

The 74VCX32373 is designed for low voltage (1.65V to

3.6V) V_CCapplications with I/O compatibility up to 3.6V.

The 74VCX32373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

■ Static Drive (I_OH/I_OL)

±24 mA @ 3.0V V_CC

±18 mA @ 2.3V V_CC

±6 mA @ 1.65V V_CC

■ Uses patented noise/EMI reduction circuitry

■ Latch-up performance exceeds 300 mA

■ ESD performance:

Human body model > 2000V

Machine model > 200V

■ Packaged in plastic Fine-Pitch Ball Grid Array (FBGA)

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V_CCthrough a pull-up resistor; the minimum

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Ordering Number Package Number

Package Description

74VCX32373GX

(Note 2)

BGA96A

96-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

Note 2: BGA package available in Tape and Reel only.

Logic Symbol

DS500567

www.fairchildsemi.com

12 3 4 5 6 7 8

中文翻译

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与74VCX32373GX相关器件

型号	品牌	获取价格	描述	数据表
74VCX32374	FAIRCHILD	获取价格	Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
74VCX32374G	FAIRCHILD	获取价格	Low Voltage 32-Bit D-Type Flip-Flops with 3.6V Tolerant Inputs and Outputs
74VCX32374GX	ROCHESTER	获取价格	ALVC/VCX/A SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96, 5.50 MM, PLASTIC, MO-205, FBGA-
74VCX32374GX	FAIRCHILD	获取价格	Bus Driver, ALVC/VCX/A Series, 4-Func, 8-Bit, True Output, CMOS, PBGA96, 5.50 MM, PLASTIC,
74VCX32500	FAIRCHILD	获取价格	Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74VCX32500G	FAIRCHILD	获取价格	Low Voltage 36-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74VCX32500GX	ETC	获取价格	18-Bit Bus Transceiver
74VCX32BQX	FAIRCHILD	获取价格	Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs
74VCX32M	FAIRCHILD	获取价格	Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs
74VCX32MTC	FAIRCHILD	获取价格	Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs

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