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74VCX16841MTDX PDF预览

74VCX16841MTDX

更新时间： 2024-09-15 23:24:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
7页 68K
描述
10-Bit D-Type Latch

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中文翻译

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74VCX16841MTDX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, MO-153, TSSOP-56
针数：56Reach Compliance Code：unknown
HTS代码：8542.39.00.01风险等级：5.71
Is Samacsys：N系列：ALVC/VCX/A
JESD-30 代码：R-PDSO-G56JESD-609代码：e3
长度：14 mm负载电容（CL）：30 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：2位数：10
功能数量：2端口数量：2
端子数量：56最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP56,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：3 ns
传播延迟（tpd）：8.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

74VCX16841MTDX 数据手册

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March 1998  
Revised April 1999  
74VCX16841  
Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant  
Inputs and Outputs  
General Description  
Features  
■ 1.65V–3.6V VCC supply operation  
The VCX16841 contains twenty non-inverting latches with  
3-STATE outputs and is intended for bus oriented applica-  
tions. The device is byte controlled. The flip-flops appear  
transparent to the data when the Latch enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup time  
is latched. Data appears on the bus when the Output  
Enable (OE) is LOW. When OE is HIGH, the outputs are in  
a high impedance state.  
■ 3.6V tolerant inputs and outputs  
■ tPD (Dn to On)  
3.0 ns max for 3.0V to 3.6V VCC  
3.4 ns max for 2.3V to 2.7V VCC  
6.8 ns max for 1.65V to 1.95V VCC  
■ Power-off high impedance inputs and outputs  
■ Supports live insertion and withdrawal (Note 1)  
The 74VCX16841 is designed for low voltage (1.65V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
The 74VCX16841 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
■ Static Drive (IOH/IOL)  
±24 mA @ 3.0V VCC  
±18 mA @ 2.3V VCC  
±6 mA @ 1.65V VCC  
■ Uses patented noise/EMI reduction circuitry  
■ Latch-up performance exceeds 300 mA  
■ ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VCX16841MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
OEn  
Description  
Output Enable Input (Active LOW)  
Latch Enable Input  
Inputs  
LEn  
D0–D19  
O0–O19  
Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS500132.prf  
www.fairchildsemi.com  
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中文翻译

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74VCX16841MTDX 替代型号

型号 品牌 替代类型 描述 数据表
74VCX16841MTD FAIRCHILD

完全替代

 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs
74ALVC16841MTDX FAIRCHILD

类似代替

 10-Bit D-Type Latch
74ALVC16841MTD FAIRCHILD

类似代替

 Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs

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