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74VCX16841_04 PDF预览

74VCX16841_04

更新时间: 2024-09-16 04:47:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
9页 146K
描述
Low Voltage 20-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs

74VCX16841_04 数据手册

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March 1998  
Revised October 2004  
74VCX16841  
Low Voltage 20-Bit Transparent Latch  
with 3.6V Tolerant Inputs and Outputs  
General Description  
Features  
1.4V to 3.6V VCC supply operation  
The VCX16841 contains twenty non-inverting latches with  
3-STATE outputs and is intended for bus oriented applica-  
tions. The device is byte controlled. The flip-flops appear  
transparent to the data when the Latch enable (LE) is  
HIGH. When LE is LOW, the data that meets the setup time  
is latched. Data appears on the bus when the Output  
Enable (OE) is LOW. When OE is HIGH, the outputs are in  
a high impedance state.  
3.6V tolerant inputs and outputs  
tPD (Dn to On)  
3.0 ns max for 3.0V to 3.6V VCC  
Power-off high impedance inputs and outputs  
Supports live insertion and withdrawal (Note 1)  
Static Drive (IOH/IOL  
)
The 74VCX16841 is designed for low voltage (1.4V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
±24 mA @ 3.0V VCC  
The 74VCX16841 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to VCC through a pull-up resistor; the minimum  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VCX16841MTD  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
LEn  
Output Enable Input (Active LOW)  
Latch Enable Input  
Inputs  
D0D19  
O0O19  
Outputs  
© 2004 Fairchild Semiconductor Corporation  
DS500132  
www.fairchildsemi.com  

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