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74VCX163245 PDF预览

74VCX163245

更新时间: 2024-11-26 22:45:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线收发器转换器电平转换器
页数 文件大小 规格书
15页 345K
描述
16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR

74VCX163245 数据手册

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74VCX163245  
16-BIT DUAL SUPPLY BUS TRANSCEIVER  
LEVEL TRANSLATOR  
TARGET DATA  
HIGH SPEED: t = 4.4ns (MAX.) at T =85°C  
PD A  
V
= 3.0V V  
= 2.3V  
CCA  
CCB  
LOW POWER DISSIPATION:  
= I = 20µA(MAX.) at T =85°C  
I
CCA  
CCB  
A
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 12mA MIN at  
OHA  
OLA  
V
= 3.0V V  
= 1.65V or 2.3V  
TSSOP  
TFBGA  
TRAY  
µTFBGA  
CCA  
CCB  
|I  
| = I  
= 8mA MIN at  
OHA  
OLA  
V
= 2.3V V  
= 1.65V)  
CCB  
CCA  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
T & R  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
TSSOP48  
74VCX163245TTR  
TFBGA54  
74VCX163245LB 74VCX163245LBR  
74VCX163245TB 74VCX163245TBR  
OPERATING VOLTAGE RANGE:  
µTFBGA42  
V
V
(OPR)=2.3Vto3.6V(1.2VDataRetention)  
(OPR)=1.65Vto2.7V(1.2VDataRetention)  
CCA  
CCB  
LOGIC DIAGRAM  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 16245  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
DESCRIPTION  
The 74VCX163245 is a dual supply low voltage  
CMOS 16-BIT BUS TRANSCEIVER fabricated  
with sub-micron silicon gate and five-layer metal  
2
wiring C MOS technology. Designed for use as an  
interface between a 3.3V bus and a 2.5V or 1.8V  
bus in a mixed 3.3V/1.8V,3.3V/2.5V and 2.5V/  
1.8V supply systems, it achieves high speed  
operation while maintaining the CMOS low power  
dissipation.  
This IC is intended for two-way asynchronous  
communication between data buses and the  
direction of data transmission is determined by  
nDIR inputs. The enable inputs nOE can be used  
to disable the device so that the buses are  
effectively isolated. The A-port interfaces with the  
3V bus, the B-port with the 2.5V and 1.8V bus.  
All inputs are equipped with protection circuits  
against static discharge, giving them 2KV ESD im-  
munity and transient excess voltage. All floating  
bus terminals during High Z State must be held  
HIGH or LOW.  
June 2003  
1/15  
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.  

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