Datasheet > 74VCX162601

74VCX162601

更新时间： 2024-11-08 22:45:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		总线收发器
页数	文件大小	规格书
8页	65K
描述
Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26ヘ Series Resistors in the B-Port Outputs

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74VCX162601 数据手册

April 1998

Revised April 1999

74VCX162601

Low Voltage 18-Bit Universal Bus Transceivers with 3.6V

Tolerant Inputs and Outputs and 26Ω Series Resistors in

the B-Port Outputs

General Description

The VCX162601, 18-bit universal bus transceiver, com-

bines D-type latches and D-type flip-flops to allow data flow

in transparent, latched, and clocked modes.

Features

■ 1.65V–3.6V V_CCsupply operation

■ 3.6V tolerant inputs and outputs

■ 26Ω series resistors in B-Port outputs

■ t_PD(A to B)

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. Output-enable OEAB is active-LOW. When OEAB

is HIGH, the outputs are in the HIGH-impedance state.

3.8 ns max for 3.0V to 3.6V V_CC

4.6 ns max for 2.3V to 2.7V V_CC

9.2 ns max for 1.65V to 1.95V V_CC

■ Power-down high impedance inputs and outputs

■ Supports live insertion/withdrawal (Note 1)

■ Static Drive (I_OH/I_OLB outputs)

±12 mA @ 3.0V V_CC

±8 mA @ 2.3V V_CC

±3 mA @ 1.65V V_CC

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

The 74VCX162601 is designed for low voltage (1.65V to

3.6V) V_CCapplications with I/O compatibility up to 3.6V.

■ Uses patented noise/EMI reduction circuitry

■ Latchup performance exceeds 300 mA

■ ESD performance:

The VCX162601 is also designed with 26Ω series resistors

in the B-Port outputs. This design reduces line noise in

applications such as memory address drivers, clock driv-

ers, and bus transceivers/transmitters.

Human body model > 2000V

Machine model >200V

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

through a pull-up resistor; the minimum

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Order Number

Package Number

Package Description

74VCX162601MTD

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Pin Descriptions

Pin Names

OEAB, OEBA

LEAB, LEBA

Description

Output Enable Inputs (Active LOW)

Latch Enable Inputs

CLKAB, CLKBA

Clock Inputs

CLKENAB, CLKENBA Clock Enable Inputs

A₁–A₁₈

Side A Inputs or 3-STATE Outputs

Side B Inputs or 3-STATE Outputs

B₁–B₁₈

DS500150.prf

www.fairchildsemi.com

12 3 4 5 6 7 8

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与74VCX162601相关器件

型号	品牌	获取价格	描述	数据表
74VCX162601_04	FAIRCHILD	获取价格	Low Voltage 18-Bit Universal Bus Transceivers
74VCX162601MTD	FAIRCHILD	获取价格	Low Voltage 18-Bit Universal Bus Transceivers
74VCX162601MTDX	FAIRCHILD	获取价格	18-Bit Bus Transceiver
74VCX162827	FAIRCHILD	获取价格	Low Voltage 20-Bit Buffer/Line Driver with 3.
74VCX162827MEAX	FAIRCHILD	获取价格	Bus Driver, ALVC/VCX/A Series, 2-Func, 10-Bit, True Output, CMOS, PDSO56
74VCX162827MTD	FAIRCHILD	获取价格	Low Voltage 20-Bit Buffer/Line Driver with 3.
74VCX162827MTDX	FAIRCHILD	获取价格	Dual 10-Bit Buffer/Driver
74VCX162827MTDX_NL	FAIRCHILD	获取价格	暂无描述
74VCX162835	FAIRCHILD	获取价格	Low Voltage 18-Bit Universal Bus Driver with
74VCX162835MTD	FAIRCHILD	获取价格	Low Voltage 18-Bit Universal Bus Driver with

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