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74VCX16244GX

更新时间： 2024-09-15 23:13:43
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路
页数 文件大小 规格书
10页 111K
描述
Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

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74VCX16244GX 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：LFBGA, BGA54,6X9,32
针数：54Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.54
控制类型：ENABLE LOW系列：ALVC/VCX/A
JESD-30 代码：R-PBGA-B54JESD-609代码：e0
长度：8 mm负载电容（CL）：30 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.024 A
湿度敏感等级：3位数：4
功能数量：4端口数量：2
端子数量：54最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA54,6X9,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：2.5 ns
传播延迟（tpd）：30 ns认证状态：Not Qualified
座面最大高度：1.4 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：1.2 V
标称供电电压 (Vsup)：1.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.5 mm
Base Number Matches：1

74VCX16244GX 数据手册

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October 1996  
Revised June 2005  
74VCX16244  
Low Voltage 16-Bit Buffer/Line Driver with  
3.6V Tolerant Inputs and Outputs  
General Description  
The VCX16244 contains sixteen non-inverting buffers with  
Features  
■ 1.2V to 3.6V VCC supply operation  
3-STATE outputs to be employed as  
a memory and  
■ 3.6V tolerant inputs and outputs  
■ tPD  
address driver, clock driver, or bus oriented transmitter/  
receiver. The device is nibble (4-bit) controlled. Each nibble  
has separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
2.5 ns max for 3.0V to 3.6V VCC  
■ Power-off high impedance inputs and outputs  
■ Supports live insertion and withdrawal (Note 1)  
The 74VCX16244 is designed for low voltage (1.2V to  
3.6V) VCC applications with I/O capability up to 3.6V.  
■ Static Drive (IOH/IOL  
)
The 74VCX16244 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
24 mA @ 3.0V VCC  
■ Uses patented noise/EMI reduction circuitry  
■ Latch-up performance exceeds 300 mA  
■ ESD performance:  
Human body model 2000V  
Machine model 200V  
■ Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA)  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VCX16244G  
(Note 2)(Note 3)  
BGA54A  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74VCX16244MTD  
(Note 3)  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 2: Ordering Code “G” indicates Tray.  
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2005 Fairchild Semiconductor Corporation  
DS012168  
www.fairchildsemi.com  
1234567...10

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74VCX16244GX 替代型号

型号 品牌 替代类型 描述 数据表
74VCX16244G FAIRCHILD

完全替代

 Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs

与74VCX16244GX相关器件

型号 品牌 获取价格 描述 数据表
74VCX16244MTD FAIRCHILD

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 		Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
74VCX16244MTD STMICROELECTRONICS

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 		16-BIT DUAL SUPPLY BUS TRANSCEIVER LEVEL TRANSLATOR WITH A SIDE SERIES RESISTOR
74VCX16244MTDX FAIRCHILD

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 		Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs
74VCX16244MTDX ONSEMI

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 		低压 1.8/2.5/3.3 V 16 位缓冲器，带 3.6 V 耐压输入和输出（3 态，
74VCX16244MTDX_NL FAIRCHILD

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 		Bus Driver, ALVC/VCX/A Series, 4-Func, 4-Bit, True Output, CMOS, PDSO48, 6.10 MM, MO-153ED
74VCX16244MTDXT ONSEMI

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 		暂无描述
74VCX16244T STMICROELECTRONICS

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 		ALVC/VCX/A SERIES, QUAD 4-BIT DRIVER, TRUE OUTPUT, PDSO48, TSSOP-48
74VCX16244TTR ONSEMI

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 		LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS
74VCX16244X FAIRCHILD

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 		暂无描述
74VCX16245 FAIRCHILD

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 		Low Voltage 16-Bit Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs

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