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74VCX132M PDF预览

74VCX132M

更新时间: 2024-09-14 22:37:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 栅极触发器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 68K
描述
Low Voltage Quad 2-Input NAND Gate with Schmitt Trigger Inputs and 3.6V Tolerant Inputs and Outputs

74VCX132M 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP, SOP14,.25针数:14
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.72Is Samacsys:N
系列:ALVC/VCX/AJESD-30 代码:R-PDSO-G14
JESD-609代码:e3长度:8.6235 mm
负载电容(CL):30 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.024 A湿度敏感等级:1
功能数量:4输入次数:2
端子数量:14最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP14,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:RAIL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:3.3 ns
传播延迟(tpd):16.4 ns认证状态:Not Qualified
施密特触发器:YES座面最大高度:1.753 mm
子类别:Gates最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):1.4 V标称供电电压 (Vsup):1.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

74VCX132M 数据手册

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July 1999  
Revised July 1999  
74VCX132  
Low Voltage Quad 2-Input NAND Gate with  
Schmitt Trigger Inputs and 3.6V Tolerant Inputs  
and Outputs  
General Description  
Features  
The VCX132 contains four 2-input NAND gates with  
Schmitt Trigger Inputs. The pin configuration and function  
are the same as the VCX00 except the inputs have hyster-  
esis between the positive-going and negative-going input  
thresholds. This hysteresis is useful for transforming slowly  
switching input signals into sharply defined, jitter-free out-  
put signals. This product should be used where noise mar-  
gin greater than that of conventional gates is required.  
1.65V-3.6V VCC supply operation  
3.6V tolerant inputs and outputs  
tPD  
3.3 ns max for 3.0V to 3.6V VCC  
4.1 ns max for 2.3V to 2.7V VCC  
8.2 ns max for 1.65V to 1.95V VCC  
Power-off high impedance inputs and outputs  
The VCX132 is designed for low voltage (1.65V to 3.6V)  
VCC applications with I/O compatibility up to 3.6V.  
Static Drive (IOH/IOL  
)
This product is fabricated with an advanced CMOS tech-  
nology to achieve high-speed operation while maintaining  
low CMOS power dissipation.  
±24 mA @ 3.0V VCC  
±18 mA @ 2.3V VCC  
±6 mA @ 1.65V VCC  
Uses patented Quiet Series noise/EMI reduction  
circuitry  
Latchup performance exceeds 300 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 250V  
Ordering Code:  
Order Number Package Number  
Package Description  
74VCX132M  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74VCX132MTC  
MTC14  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Diagram  
Connection Diagram  
Pin Descriptions  
Pin Name  
An, Bn  
Description  
Inputs  
Outputs  
On  
Quiet Series is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
ds500164  
www.fairchildsemi.com  

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