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74V2T70 PDF预览

74V2T70

更新时间: 2024-09-12 21:53:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
7页 126K
描述
TRIPLE BUFFER

74V2T70 数据手册

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74V2T70  
TRIPLE BUFFER  
HIGH SPEED: t = 3.6ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T = 25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN), V = 0.8V (MAX)  
V
IH  
IL  
POWER DOWN PROTECTION ON INPUT  
SOT23-8L  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8mA (MIN) at V = 4.5V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
PACKAGE  
t
t
PLH  
PHL  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
SOT23-8L  
74V2T70STR  
V
CC  
IMPROVED LATCH-UP IMMUNITY  
The internal circuit is composed of 2 stages  
including buffer output, which provide high noise  
immunity and stable output.  
DESCRIPTION  
The 74V2T70 is an advanced high-speed CMOS  
TRIPLE BUFFER fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
Power down protection is provided on input and 0  
to 7V can be accepted on input with no regard to  
the supply voltage. This device can be used to  
interface 5V to 3V.  
2
technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
June 2003  
1/7  

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