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74V2T125 PDF预览

74V2T125

更新时间: 2024-02-09 08:55:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
10页 215K
描述
DUAL BUS BUFFER (3-STATE)

74V2T125 数据手册

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74V2T125  
DUAL BUS BUFFER (3-STATE)  
PRELIMINARY DATA  
HIGH SPEED: t = 3.8ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T =25°C  
CC  
A
COMPATIBLE WITH TTL OUTPUTS:  
= 2V (MIN), V = 0.8V (MAX)  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
V
IH  
IL  
SOT23-8L  
SOT323-8L  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
t
t
PLH  
PHL  
PACKAGE  
OPERATING VOLTAGE RANGE:  
(OPR) = 4.5V to 5.5V  
SOT23-8L  
74V2T125STR  
74V2T125CTR  
V
CC  
SOT323-8L  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74V2T125 is an advanced high-speed CMOS  
DUAL BUS BUFFER fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
tecnology.  
inputs with no regard to the supply voltage. This  
device can be used to interface 3V to 5V systems  
and it is ideal for portable applications like  
personal digital assistant, camcorder and all  
battery-powered equipment.  
2
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them ESD immunity and transient excess voltage.  
3-STATE control input nG has to be set HIGH to  
place the output into the high impedance state.  
Power down protection is provided on all inputs  
and outputs and 0 to 7V can be accepted on  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
December 2001  
1/10  
This is preliminary information on a new product now in development are or undergoing evaluation. Details subject to change without notice.  

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