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74V1T70 PDF预览

74V1T70

更新时间: 2024-11-03 22:45:59
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
7页 49K
描述
SINGLE BUFFER

74V1T70 数据手册

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74V1T70  
SINGLE BUFFER  
PRELIMINARY DATA  
HIGH SPEED:tPD =5.5ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
I
CC =1 µA (MAX.) at TA =25 oC  
COMPATIBLEWITH TTL OUTPUTS:  
VIH =2V (MIN), VIL = 0.8V(MAX)  
POWERDOWN PROTECTIONON INPUT  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
S
C
(SOT23-5L)  
(SC-70)  
ORDER CODE:  
74V1T70S 74V1T70C  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 4.5V to 5.5V  
The internal circuit is composed of 2 stages  
including buffer output, which provide high noise  
immunity and stable output.  
IMPROVED LATCH-UP IMMUNITY  
Power down protection is provided on input and 0  
to 7V can be accepted on input with no regard to  
the supply voltage. This device can be used to  
interface5V to 3V.  
DESCRIPTION  
The 74V1T70 is an advanced high-speed CMOS  
SINGLE BUFFER fabricated with sub-micron  
silicon gate and double-layermetal wiring C2MOS  
technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/7  
October 1999  

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