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74V1G03CTR PDF预览

74V1G03CTR

更新时间: 2024-11-05 03:07:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 栅极触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
9页 115K
描述
SINGLE 2-INPUT OPEN DRAIN NAND GATE

74V1G03CTR 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:SC-70包装说明:SOT-323, 5 PIN
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.84
Is Samacsys:N系列:74V
JESD-30 代码:R-PDSO-G5JESD-609代码:e3
长度:2 mm负载电容(CL):50 pF
逻辑集成电路类型:NAND GATE最大I(ol):0.004 A
湿度敏感等级:1功能数量:1
输入次数:2端子数量:5
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/5.5 VProp。Delay @ Nom-Sup:11 ns
传播延迟(tpd):11 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:MATTE TIN
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.25 mmBase Number Matches:1

74V1G03CTR 数据手册

 浏览型号74V1G03CTR的Datasheet PDF文件第2页浏览型号74V1G03CTR的Datasheet PDF文件第3页浏览型号74V1G03CTR的Datasheet PDF文件第4页浏览型号74V1G03CTR的Datasheet PDF文件第5页浏览型号74V1G03CTR的Datasheet PDF文件第6页浏览型号74V1G03CTR的Datasheet PDF文件第7页 
74V1G03  
SINGLE 2-INPUT OPEN DRAIN NAND GATE  
HIGH SPEED: t = 3.9ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUTS  
OPERATING VOLTAGE RANGE:  
SOT23-5L  
SOT323-5L  
T & R  
V
(OPR) = 2V to 5.5V  
CC  
IMPROVED LATCH-UP IMMUNITY  
ORDER CODES  
PACKAGE  
DESCRIPTION  
SOT23-5L  
74V1G03STR  
74V1G03CTR  
The 74V1G03 is an advanced high-speed CMOS  
SINGLE 2-INPUT OPEN DRAIN NAND GATE  
fabricated with sub-micron silicon gate and  
SOT323-5L  
2
double-layer metal wiring C MOS technology.  
can also be used as a led driver in any other  
application requiring current sink.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
immunity and stable output.  
The device can, with an external pull-up resistor,  
be used in wired AND configuration. This device  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2004  
1/9  

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