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74V1G00CTR PDF预览

74V1G00CTR

更新时间: 2024-11-05 03:07:47
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
9页 112K
描述
SINGLE 2-INPUT NAND GATE

74V1G00CTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SC-70
包装说明:TSSOP, TSSOP6,.08针数:5
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:16 weeks风险等级:5.31
系列:74VJESD-30 代码:R-PDSO-G5
JESD-609代码:e4长度:2 mm
负载电容(CL):50 pF逻辑集成电路类型:NAND GATE
最大I(ol):0.004 A湿度敏感等级:1
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP6,.08
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:2/5.5 VProp。Delay @ Nom-Sup:11.5 ns
传播延迟(tpd):11.5 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.1 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.25 mmBase Number Matches:1

74V1G00CTR 数据手册

 浏览型号74V1G00CTR的Datasheet PDF文件第2页浏览型号74V1G00CTR的Datasheet PDF文件第3页浏览型号74V1G00CTR的Datasheet PDF文件第4页浏览型号74V1G00CTR的Datasheet PDF文件第5页浏览型号74V1G00CTR的Datasheet PDF文件第6页浏览型号74V1G00CTR的Datasheet PDF文件第7页 
74V1G00  
SINGLE 2-INPUT NAND GATE  
HIGH SPEED: t = 3.7ns (TYP.) at V = 5V  
PD CC  
LOW POWER DISSIPATION:  
I
= 1µA(MAX.) at T =25°C  
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOT23-5L  
SOT323-5L  
T & R  
|I | = I = 8mA (MIN) at V = 4.5V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
PACKAGE  
V
CC  
SOT23-5L  
74V1G00STR  
74V1G00CTR  
IMPROVED LATCH-UP IMMUNITY  
SOT323-5L  
DESCRIPTION  
The 74V1G00 is an advanced high-speed CMOS  
SINGLE 2-INPUT NAND GATE fabricated with  
sub-micron silicon gate and double-layer metal  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V.  
2
wiring C MOS technology.  
The internal circuit is composed of 3 stages  
including buffer output, which provide high noise  
immunity and stable output.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2004  
1/9  

74V1G00CTR 替代型号

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