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74LX1G32STR PDF预览

74LX1G32STR

更新时间: 2024-11-10 21:58:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器逻辑集成电路光电二极管输入元件
页数 文件大小 规格书
10页 119K
描述
LOW VOLTAGE CMOS SINGLE 2-INPUT OR GATE WITH 5V TOLERANT INPUT

74LX1G32STR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOT-23
包装说明:SOT-23, 5 PIN针数:5
Reach Compliance Code:compliantHTS代码:8542.39.00.01
Factory Lead Time:16 weeks风险等级:5.41
Is Samacsys:N系列:TTL/H/L
JESD-30 代码:R-PDSO-G5JESD-609代码:e4
长度:2.9 mm负载电容(CL):50 pF
逻辑集成电路类型:OR GATE最大I(ol):0.024 A
功能数量:1输入次数:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSOP5/6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:5.2 ns
传播延迟(tpd):13 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:1.45 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1.625 mmBase Number Matches:1

74LX1G32STR 数据手册

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74LX1G32  
LOW VOLTAGE CMOS SINGLE 2-INPUT OR GATE  
WITH 5V TOLERANT INPUT  
5V TOLERANT INPUTS  
HIGH SPEED: t = 4.7ns (MAX.) at V = 3V  
PD  
CC  
LOW POWER DISSIPATION:  
I
= 1µA (MAX.) at T = 25°C  
CC  
A
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SOT23-5  
SC70-5  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 24mA (MIN) at V = 3V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
ORDER CODES  
t
t
PLH  
PHL  
PACKAGE  
T & R  
OPERATING VOLTAGE RANGE:  
(OPR) = 1.65V to 5.5V  
V
SOT23-5L  
74LX1G32STR  
74LX1G32CTR  
CC  
(1.2V Data Retention)  
SOT323-5L  
IMPROVED LATCH-UP IMMUNITY  
output, which provide high noise immunity and  
stable output.  
DESCRIPTION  
The 74LX1G32 is a low voltage CMOS SINGLE  
2-INPUT OR GATE fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology.  
It is ideal for 1.65 to 5.5 V  
Power down protection is provided on input and  
output and 0 to 7V can be accepted on inputs with  
no regard to the supply voltage. It can be  
interfaced to 5V signal environment for inputs in  
mixed 3.3/5V system.  
2
operations and low  
CC  
power and low noise applications. The internal  
circuit is composed of 3 stages including buffer  
All inputs and outputs are equipped with  
protection circuits against static discharge.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2004  
1/10  

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