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74LX1G125STR PDF预览

74LX1G125STR

更新时间: 2024-02-16 05:13:39
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 150K
描述
SINGLE BUS BUFFER (3-STATE)

74LX1G125STR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOT-23包装说明:SOT-23, 5 PIN
针数:5Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.83
Is Samacsys:N控制类型:ENABLE LOW
系列:TTL/H/LJESD-30 代码:R-PDSO-G5
JESD-609代码:e3长度:2.9 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.024 A位数:1
功能数量:1端口数量:2
端子数量:5最高工作温度:125 °C
最低工作温度:-55 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSOP5/6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
Prop。Delay @ Nom-Sup:6.2 ns传播延迟(tpd):12 ns
认证状态:Not Qualified座面最大高度:1.45 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:TIN
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.625 mmBase Number Matches:1

74LX1G125STR 数据手册

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74LX1G125  
SINGLE BUS BUFFER (3-STATE)  
5V TOLERANT INPUTS  
HIGH SPEED: t = 4.7ns (MAX.) at V = 3V  
PD  
CC  
LOW POWER DISSIPATION:  
I
= 1µA (MAX.) at T = 25°C  
CC  
A
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
SOT23-5L  
SOT323-5L  
|I | = I = 24mA (MIN) at V = 3V  
OH  
OL  
CC  
BALANCED PROPAGATION DELAYS:  
t
t
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 1.65V to 5.5V  
V
CC  
Flip-Chip5  
(Max dim = 1.3x1.3mm)  
(1.2V Data Retention)  
LATCH-UP PERFORMANCE EXCEED  
300mA  
ORDER CODES  
RoHS FLIP-CHIP AND SOT PACKAGES  
PACKAGE  
T & R  
DESCRIPTION  
The 74LX1G125 is a low voltage CMOS SINGLE  
BUS BUFFER fabricated with sub-micron silicon  
SOT23-5L  
SOT323-5L  
Flip-Chip5  
74LX1G125STR  
74LX1G125CTR  
74LX1G125BJR  
2
gate and double-layer metal wiring C MOS  
technology.  
allow ultra low power consumption and guarantee  
optimized operations between 2.8V and 1.8V  
system, as Smart Phone, Digital Still Camera,  
PDA, Notebook, or each other battery powered  
equipment.  
3-STATE control input G has to be set HIGH to  
place the output into the high impedance state.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface 5V to 3V or lower power supply  
systems. The sub-micron CMOS technology used  
All inputs and outputs are equipped with  
protection circuits against ESD discharge.  
PIN CONNECTION AND IEC LOGIC SYMBOLS (top view for SOT, top through view for Flip-Chip)  
April 2004  
1/13  

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