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74LVX573 PDF预览

74LVX573

更新时间: 2024-11-13 22:12:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
7页 95K
描述
Low Voltage Octal Latch with 3-STATE Outputs

74LVX573 数据手册

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June 1993  
Revised April 2005  
74LVX573  
Low Voltage Octal Latch with 3-STATE Outputs  
General Description  
Features  
The LVX573 is a high-speed octal latch with buffered com-  
mon Latch Enable (LE) and buffered common Output  
Enable (OE) inputs. The LVX573 is functionally identical to  
the LVX373 but with inputs and outputs on opposite sides  
of the package. The inputs tolerate up to 7V allowing inter-  
face of 5V systems to 3V systems.  
Input voltage translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX573M  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX573SJ  
74LVX573MTC  
MTC20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
D0D7  
LE  
Data Inputs  
Latch Enable Input  
OE  
3-STATE Output Enable Input  
3-STATE Latch Outputs  
O0O7  
© 2005 Fairchild Semiconductor Corporation  
DS011616  
www.fairchildsemi.com  

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