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74LVX541MX PDF预览

74LVX541MX

更新时间: 2024-02-26 23:27:30
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
6页 86K
描述
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

74LVX541MX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOP
包装说明:5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20针数:20
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.64
Is Samacsys:N其他特性:WITH DUAL OUTPUT ENABLE
控制类型:ENABLE LOW系列:LV/LV-A/LVX/H
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.6 mm逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:12 ns传播延迟(tpd):17 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

74LVX541MX 数据手册

 浏览型号74LVX541MX的Datasheet PDF文件第2页浏览型号74LVX541MX的Datasheet PDF文件第3页浏览型号74LVX541MX的Datasheet PDF文件第4页浏览型号74LVX541MX的Datasheet PDF文件第5页浏览型号74LVX541MX的Datasheet PDF文件第6页 
September 1999  
Revised April 2005  
74LVX541  
Low Voltage Octal Buffer/Line Driver with  
3-STATE Outputs  
General Description  
Features  
Input voltage translation from 5V to 3V  
The LVX541 is an octal non-inverting buffer and line driver  
designed to be employed as a memory address driver,  
clock driver and bus oriented transmitter or receiver which  
provides improved PC board density. The inputs tolerate up  
to 7V allowing interface of 5V systems to 3V systems.  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX541M  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX541SJ  
74LVX541MTC  
MTC20  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Connection Diagram  
Logic Symbol  
IEEE/IEC  
Pin Descriptions  
Truth Table  
Inputs  
OE2  
Pin Names  
Descriptions  
Outputs  
OE1  
I
OE1, OE2  
3-STATE Output Enable Inputs  
Inputs  
L
H
X
L
L
X
H
L
H
X
X
L
H
Z
Z
L
I
0 - I7  
O0 - O7  
3-STATE Outputs  
H
L
HIGH Voltage Level  
LOW Voltage Level  
X
Z
Immaterial  
High Impedance  
© 2005 Fairchild Semiconductor Corporation  
DS500291  
www.fairchildsemi.com  

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