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74LVX373 PDF预览

74LVX373

更新时间: 2024-11-14 22:12:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
7页 94K
描述
Low Voltage Octal Transparent Latch with 3-STATE Outputs

74LVX373 数据手册

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June 1993  
Revised April 2005  
74LVX373  
Low Voltage Octal Transparent Latch with  
3-STATE Outputs  
General Description  
Features  
Input voltage translation from 5V to 3V  
The LVX373 consists of eight latches with 3-STATE outputs  
for bus organized system applications. The latches appear  
transparent to the data when Latch Enable (LE) is HIGH.  
When LE is LOW, the data satisfying the input timing  
requirements is latched. Data appears on the bus when the  
Output Enable (OE) is LOW. When OE is HIGH, the bus  
output is in the high impedance state. The inputs tolerate  
up to 7V allowing interface of 5V systems to 3V systems.  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX373M  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVX373SJ  
74LVX373MTC  
MTC20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JEDED J-STD-020B.  
Logic Symbols  
Pin Descriptions  
Pin Names  
D0D7  
Description  
Data Inputs  
LE  
Latch Enable Input  
OE  
Output Enable Input  
3-STATE Latch Outputs  
IEEE/IEC  
O0O7  
Truth Table  
Inputs  
Outputs  
On  
Dn  
LE  
X
OE  
H
L
X
L
Z
L
H
H
L
L
H
X
H
Connection Diagram  
L
O0  
H
L
Z
X
O
HIGH Voltage Level  
LOW Voltage Level  
High Impedance  
Immaterial  
Previous O before HIGH-to-LOW transition of Latch Enable  
0
0
© 2005 Fairchild Semiconductor Corporation  
DS011613  
www.fairchildsemi.com  

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