74LVX245

更新时间： 2024-11-09 04:47:59

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		总线收发器输入元件
页数	文件大小	规格书
12页	308K
描述
LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER (3-STATE) WITH 5V TOLERANT INPUTS

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74LVX245 数据手册

74LVX245

LOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER

(3-STATE) WITH 5V TOLERANT INPUTS

■

HIGH SPEED:

=4.7ns (TYP.) at V = 3.3V

■

5V TOLERANT INPUTS

POWER-DOWN PROTECTION ON INPUTS

INPUT VOLTAGE LEVEL:

= 0.8V, V = 2V at V =3V

IH CC

SOP

TSSOP

■

LOW POWER DISSIPATION:

= 4 µA (MAX.) at T =25°C

LOW NOISE:

= 0.5V (TYP.) at V =3.3V

Table 1: Order Codes

PACKAGE

OLP

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4 mA (MIN) at V =3V

T & R

SOP

74LVX245MTR

74LVX245TTR

BALANCED PROPAGATION DELAYS:

TSSOP

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

DIR input. The enable input G can be used to

disable the device so that the busses are

effectively isolated.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

This device can be used to interface 5V to 3V. It

combines high speed performance with the true

CMOS low power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 245

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVX245 is a low voltage CMOS OCTAL

BUS BUFFER (3-STATE) fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology. It is ideal for low

power, battery operated and low noise 3.3V

applications.

This IC is intended for two-way asynchronous

communication between data busses; the

direction of data transmission is determined by

All floating bus terminals during High Z state must

be held HIGH or LOW.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 5

1/12

August 2004

12 3 4 5 6 7...12

中文翻译

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