74LVX240TTR

更新时间： 2024-02-17 10:05:58

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
12页	262K
描述
LOW VOLTAGE CMOS OCTAL BUS BUFFER (3-STATE INV.) WITH 5V TOLERANT INPUTS

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74LVX240TTR 数据手册

74LVX240

LOW VOLTAGE CMOS OCTAL BUS BUFFER (3-STATE INV.)

WITH 5V TOLERANT INPUTS

■

HIGH SPEED:

=4.7ns (TYP.) at V = 3.3V

■

5V TOLERANT INPUTS

POWER-DOWN PROTECTION ON INPUTS

INPUT VOLTAGE LEVEL:

= 0.8V, V = 2V at V =3V

IH CC

SOP

TSSOP

■

LOW POWER DISSIPATION:

= 4 µA (MAX.) at T =25°C

LOW NOISE:

= 0.3V (TYP.) at V =3.3V

Table 1: Order Codes

PACKAGE

OLP

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 4 mA (MIN) at V =3V

T & R

SOP

74LVX240MTR

74LVX240TTR

BALANCED PROPAGATION DELAYS:

TSSOP

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 3.6V (1.2V Data Retention)

G output enable governs four BUS BUFFERs

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 240

IMPROVED LATCH-UP IMMUNITY

This device can be used to interface 5V to 3V. It

combines high speed performance with the true

CMOS low power consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74LVX240 is a low voltage CMOS OCTAL

BUS BUFFER (3-STATE) fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology. It is ideal for low

power, battery operated and low noise 3.3V

applications.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 3

1/12

August 2004

12 3 4 5 6 7...12

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74LVX240TTR 替代型号

型号	品牌	替代类型	描述	数据表
MC74LVX240DTR2G	ONSEMI	功能相似	Octal Bus Buffer

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