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74LVX240 PDF预览

74LVX240

更新时间: 2024-01-27 20:46:20
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
5页 77K
描述
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

74LVX240 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:5.30 MM, LEAD FREE, EIAJ TYPE2, SOP-20
针数:20Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.12
Is Samacsys:N控制类型:ENABLE LOW
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G20
JESD-609代码:e3长度:12.6 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.004 A湿度敏感等级:1
位数:4功能数量:2
端口数量:2端子数量:20
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP20,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:11 ns传播延迟(tpd):16 ns
认证状态:Not Qualified座面最大高度:2.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:5.3 mmBase Number Matches:1

74LVX240 数据手册

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May 1993  
Revised March 1999  
74LVX240  
Low Voltage Octal Buffer/Line Driver with  
3-STATE Outputs  
General Description  
Features  
Input voltage translation from 5V to 3V  
The LVX240 is an octal inverting buffer and line driver  
designed to be employed as a memory address driver,  
clock driver and bus oriented transmitter or receiver which  
provides improved PC board density. The inputs tolerate  
up to 7V allowing interface of 5V systems to 3V systems.  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX240M  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-130, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LVX240SJ  
74LVX240MTC  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
IEEE/IEC  
Pin Names  
OE1, OE2  
I0–I7  
Description  
3-STATE Output Enable Inputs  
Inputs  
O0–O7  
Outputs  
Truth Tables  
Inputs  
Outputs  
(Pins 12, 14, 16, 18)  
OE1  
In  
L
L
L
H
X
H
L
Connection Diagram  
H
Z
Inputs  
Outputs  
(Pins 3, 5, 7, 9)  
OE2  
In  
L
L
L
H
X
H
L
H
Z
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
Z = High Impedance  
© 1999 Fairchild Semiconductor Corporation  
DS011609.prf  
www.fairchildsemi.com  

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