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74LVX20MTR PDF预览

74LVX20MTR

更新时间: 2024-11-04 22:15:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 输入元件
页数 文件大小 规格书
8页 155K
描述
LOW VOLTAGE CMOS DUAL 4-INPUT NAND GATE WITH 5V TOLERANT INPUTS

74LVX20MTR 数据手册

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74LVX20  
LOW VOLTAGE CMOS DUAL 4-INPUT NAND GATE  
WITH 5V TOLERANT INPUTS  
HIGH SPEED :  
= 4.1ns (TYP.) at V = 3.3V  
t
PD  
CC  
5V TOLERANT INPUTS  
INPUT VOLTAGE LEVEL :  
V =0.8V, V =2V at V =3V  
IL  
IH  
CC  
LOW POWER DISSIPATION:  
= 2 µA (MAX.) at T =25°C  
SOP  
TSSOP  
I
CC  
A
LOW NOISE:  
= 0.3V (TYP.) at V = 3.3V  
V
OLP  
CC  
ORDER CODES  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
TUBE  
T & R  
OH  
OL  
SOP  
74LVX20M  
74LVX20MTR  
74LVX20TTR  
BALANCED PROPAGATION DELAYS:  
TSSOP  
t
t
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
V
CC  
The internal circuit is composed of 3 stages  
including buffer output, which provides high noise  
immunity and stable output.  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 20  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage.  
IMPROVED LATCH-UP IMMUNITY  
POWER DOWN PROTECTION ON INPUTS  
This device can be used to interface 5V to 3V  
system. It combines high speed performance with  
the true CMOS low power consumption.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74LVX20 is a low voltage CMOS DUAL  
4-INPUT NAND GATE fabricated with sub-micron  
silicon gate and double-layer metal wiring C MOS  
technology. It is ideal for low power, battery  
operated and low noise 3.3V applications.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/8  

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