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74LVX174SJ PDF预览

74LVX174SJ

更新时间: 2024-01-11 21:21:26
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 61K
描述
Low Voltage Hex D-Type Flip-Flop with Master Reset

74LVX174SJ 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-16针数:16
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.22Is Samacsys:N
系列:LV/LV-A/LVX/HJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大I(ol):0.004 A湿度敏感等级:3
位数:6功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:15.5 ns传播延迟(tpd):22 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):2.7 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:4.4 mm
最小 fmax:95 MHzBase Number Matches:1

74LVX174SJ 数据手册

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May 1993  
Revised March 1999  
74LVX174  
Low Voltage Hex D-Type Flip-Flop with Master Reset  
General Description  
Features  
The LVX174 is a high-speed hex D flip-flop. The device is  
used primarily as a 6-bit edge-triggered storage register.  
The information on the D inputs is transferred to storage  
during the LOW-to-HIGH clock transition. The device has a  
Master Reset to simultaneously clear all flip-flops.  
Input voltage level translation from 5V to 3V  
Ideal for low power/low noise 3.3V applications  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVX174M  
M16A  
M16D  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LVX174SJ  
74LVX174MTC  
MTC16  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
D0–D5  
CP  
Data Inputs  
Clock Pulse Input  
Master Reset Input  
Outputs  
MR  
Q0–Q5  
© 1999 Fairchild Semiconductor Corporation  
DS011607.prf  
www.fairchildsemi.com  

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