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74LVX161284MTD_NL PDF预览

74LVX161284MTD_NL

更新时间： 2024-11-11 13:04:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
11页 116K
描述
Line Transceiver, 13 Func, 14 Driver, 13 Rcvr, CMOS, PDSO48, 6.10 MM, LEAD FREE, MO-153, TSSOP-48

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74LVX161284MTD_NL 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：6.10 MM, LEAD FREE, MO-153, TSSOP-48针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.16
Is Samacsys：N其他特性：CONTAINS EIGHT BIDIRECTIONAL DATA BUFFERS
差分输出：NO驱动器位数：14
输入特性：SCHMITT TRIGGER接口集成电路类型：LINE TRANSCEIVER
接口标准：IEEE 1284JESD-30 代码：R-PDSO-G48
JESD-609代码：e3/e4长度：12.5 mm
功能数量：13端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：Not Qualified最大接收延迟：44 ns
接收器位数：13座面最大高度：1.2 mm
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V电源电压1-最大：5.5 V
电源电压1-分钟：3 V电源电压1-Nom：3.15 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN/NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL最大传输延迟：44 ns
宽度：6.1 mmBase Number Matches：1

74LVX161284MTD_NL 数据手册

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January 1999  
Revised June 2005  
74LVX161284  
Low Voltage IEEE 161284 Translating Transceiver  
General Description  
Features  
■ Supports IEEE 1284 Level 1 and Level 2 signaling  
standards for bidirectional parallel communications  
between personal computers and printing peripherals  
The LVX161284 contains eight bidirectional data buffers  
and eleven control/status buffers to implement  
a full  
IEEE 1284 compliant interface. The device supports the  
IEEE 1284 standard and is intended to be used in an  
Extended Capabilities Port mode (ECP). The pinout allows  
for easy connection from the Peripheral (A-side) to the  
Host (cable side).  
■ Translation capability allows outputs on the cable side to  
interface with 5V signals  
■ All inputs have hysteresis to provide noise margin  
■ B and Y output resistance optimized to drive external  
cable  
Outputs on the cable side can be configured to be either  
open drain or high drive ( 14 mA) and are connected to a  
separate power supply pin (VCC-cable) to allow these out-  
■ B and Y outputs in high impedance mode during power  
down  
puts to be driven by a higher supply voltage than the A-  
side. The pull-up and pull-down series termination resis-  
tance of these outputs on the cable side is optimized to  
drive an external cable. In addition, all inputs (except HLH)  
and outputs on the cable side contain internal pull-up resis-  
tors connected to the VCC-cable supply to provide proper  
■ Inputs and outputs on cable side have internal pull-up  
resistors  
■ Flow-through pin configuration allows easy interface  
between the “Peripheral and Host”  
■ Replaces the function of two (2) 74ACT1284 devices  
termination and pull-ups for open drain mode.  
Outputs on the Peripheral side are standard low-drive  
CMOS outputs designed to interface with 3V logic. The DIR  
input controls data flow on the A1–A8/B1–B8 transceiver  
pins.  
Ordering Code  
Order Number  
74LVX161284MEA  
74LVX161284MTD  
Package Number  
MS48A  
Package Description  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
HD  
Description  
High Drive Enable Input (Active HIGH)  
Direction Control Input  
Inputs or Outputs  
DIR  
A1–A8  
B1–B8  
A9–A13  
Y9–Y13  
Inputs or Outputs  
Inputs  
Outputs  
A
14–A17  
Outputs  
C14–C17  
PLHIN  
PLH  
Inputs  
Peripheral Logic HIGH Input  
Peripheral Logic HIGH Output  
Host Logic HIGH Input  
Host Logic HIGH Output  
HLHIN  
HLH  
© 2005 Fairchild Semiconductor Corporation  
DS500202  
www.fairchildsemi.com  
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