Datasheet > 74LVTH574D,118

74LVTH574D,118

更新时间： 2024-11-29 09:17:11

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
17页	132K
描述
74LVT(H)574 - 3.3 V octal D-type flip-flop; 3-state SOP 20-Pin

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74LVTH574D,118 数据手册

74LVT574; 74LVTH574

3.3 V octal D-type flip-flop; 3-state

Rev. 7 — 22 November 2011

Product data sheet

1. General description

The 74LVT574; 74LVTH574 is a high-performance product designed for V_CCoperation at

3.3 V.

This device is an 8-bit, edge triggered register coupled to eight 3-state output buffers. The

two sections of the device are controlled independently by the clock (pin CP) and output

enable (pin OE) control gates. The state of each Dn input (one setup time before the

LOW-to-HIGH clock transition) is transferred to the corresponding flip-flops Qn output.

The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS

memories, or MOS microprocessors.

The active LOW output enable (pin OE) controls all eight 3-state buffers independent of

the clock operation.

When pin OE is LOW, the stored data appears at the outputs. When pin OE is HIGH, the

outputs are in the high-impedance OFF-state, which means they will neither drive nor load

the bus.

2. Features and benefits

 Inputs and outputs arranged for easy interfacing to microprocessors

 3-state outputs for bus interfacing

 Common output enable control

 TTL input and output switching levels

 Input and output interface capability to systems at 5 V supply

 Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs

 Live insertion and extraction permitted

 No bus current loading when output is tied to 5 V bus

 Power-up reset

 Power-up 3-state

 Latch-up protection

 JESD78 class II exceeds 500 mA

 ESD protection:

 HBM JESD22-A114E exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Specified from 40 C to +85 C

12 3 4 5 6 7...17

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