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74LVTH543

更新时间: 2024-11-24 22:56:23
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飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 69K
描述
Low Voltage Octal Registered Transceiver with 3-STATE Outputs

74LVTH543 数据手册

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April 2000  
Revised April 2000  
74LVTH543  
Low Voltage Octal Registered Transceiver  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVTH543 octal transceiver contains two sets of D-type  
latches for temporary storage of data flowing in either  
direction. Separate Latch Enable and Output Enable inputs  
are provided for each register to permit independent con-  
trol of inputting and outputting in either direction of data  
flow.  
5V VCC  
Bushold data inputs eliminate the need for external pull-  
up resistors to hold unused inputs  
Live insertion/extraction permitted  
Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH543 data inputs include bushold, eliminating the  
need for external pull-up resistors to hold unused inputs.  
Outputs source/sink 32 mA/+64 mA  
This octal registered transceiver is designed for low-volt-  
age (3.3V) VCC applications, but with the capability to pro-  
Functionally compatible with the 74 series 543  
Latch-up performance exceeds 500 mA  
vide a TTL interface to a 5V environment. The LVTH543 is  
fabricated with an advanced BiCMOS technology to  
achieve high speed operation similar to 5V ABT while  
maintaining a low power dissipation.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVTH543WM  
M24B  
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVTH543MTC  
MTC24  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Names  
OEAB, OEBA  
Description  
Output Enable Inputs  
Latch Enable Inputs  
Chip Enable Inputs  
Side A Inputs or  
LEAB, LEBA  
CEAB, CEBA  
A0–A7  
3-STATE Outputs  
Side B Inputs or  
B0–B7  
3-STATE Outputs  
© 2000 Fairchild Semiconductor Corporation  
DS012448  
www.fairchildsemi.com  

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