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74LVTH373SJ PDF预览

74LVTH373SJ

更新时间: 2024-11-24 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
7页 71K
描述
Low Voltage Octal Transparent Latch with 3-STATE Outputs

74LVTH373SJ 数据手册

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September 1999  
Revised October 1999  
74LVT373 • 74LVTH373  
Low Voltage Octal Transparent Latch  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVT373 and LVTH373 consist of eight latches with  
3-STATE outputs for bus organized system applications.  
The latches appear transparent to the data when Latch  
Enable (LE) is HIGH. When LE is LOW, the data satisfying  
the input timing requirements is latched. Data appears on  
the bus when the Output Enable (OE) is LOW. When OE is  
HIGH, the bus output is in a high impedance state.  
5V VCC  
Bushold data inputs eliminate the need for external pull-  
up resistors to hold unused inputs (74LVTH373), also  
available without bushold feature (74LVT373).  
Live insertion/extraction permitted  
Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH373 data inputs include bushold, eliminating the  
need for external pull-up resistors to hold unused inputs.  
Outputs source/sink 32 mA/+64 mA  
These octal latches are designed for low-voltage (3.3V)  
VCC applications, but with the capability to provide a TTL  
Functionally compatible with the 74 series 373  
interface to a 5V environment. The LVT373 and LVTH373  
are fabricated with an advanced BiCMOS technology to  
achieve high speed operation similar to 5V ABT while  
maintaining low power dissipation.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVT373WM  
74LVT373SJ  
M20B  
M20D  
MTC20  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LVT373MTC  
74LVTH373WM  
74LVTH373SJ  
74LVTH373MTC  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20D  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Logic Symbols  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS012015  
www.fairchildsemi.com  

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