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74LVTH373MTC PDF预览

74LVTH373MTC

更新时间： 2024-09-15 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
7页 71K
描述
Low Voltage Octal Transparent Latch with 3-STATE Outputs

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中文翻译

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74LVTH373MTC 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：TSSOP
包装说明：TSSOP, TSSOP20,.25针数：20
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.14
系列：LVTJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：8
功能数量：1端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP20,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：RAIL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：4.5 ns
传播延迟（tpd）：5 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

74LVTH373MTC 数据手册

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September 1999  
Revised October 1999  
74LVT373 • 74LVTH373  
Low Voltage Octal Transparent Latch  
with 3-STATE Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT373 and LVTH373 consist of eight latches with  
3-STATE outputs for bus organized system applications.  
The latches appear transparent to the data when Latch  
Enable (LE) is HIGH. When LE is LOW, the data satisfying  
the input timing requirements is latched. Data appears on  
the bus when the Output Enable (OE) is LOW. When OE is  
HIGH, the bus output is in a high impedance state.  
5V VCC  
■ Bushold data inputs eliminate the need for external pull-  
up resistors to hold unused inputs (74LVTH373), also  
available without bushold feature (74LVT373).  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH373 data inputs include bushold, eliminating the  
need for external pull-up resistors to hold unused inputs.  
■ Outputs source/sink −32 mA/+64 mA  
These octal latches are designed for low-voltage (3.3V)  
VCC applications, but with the capability to provide a TTL  
■ Functionally compatible with the 74 series 373  
interface to a 5V environment. The LVT373 and LVTH373  
are fabricated with an advanced BiCMOS technology to  
achieve high speed operation similar to 5V ABT while  
maintaining low power dissipation.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVT373WM  
74LVT373SJ  
M20B  
M20D  
MTC20  
M20B  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LVT373MTC  
74LVTH373WM  
74LVTH373SJ  
74LVTH373MTC  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
M20D  
MTC20  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Logic Symbols  
IEEE/IEC  
© 1999 Fairchild Semiconductor Corporation  
DS012015  
www.fairchildsemi.com  
1234567

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74LVTH373MTC 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH373PW TI

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