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74LVTH240SJX PDF预览

74LVTH240SJX

更新时间： 2024-09-15 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
8页 106K
描述
Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

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中文翻译

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74LVTH240SJX 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP20,.3
针数：20Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.17
控制类型：ENABLE LOW系列：LVT
JESD-30 代码：R-PDSO-G20JESD-609代码：e3
长度：12.6 mm负载电容（CL）：50 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：4
功能数量：2端口数量：2
端子数量：20最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.3
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：4 ns
传播延迟（tpd）：4.6 ns认证状态：Not Qualified
座面最大高度：2.1 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.3 mm
Base Number Matches：1

74LVTH240SJX 数据手册

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July 1999  
Revised March 2005  
74LVT240 • 74LVTH240  
Low Voltage Octal Buffer/Line Driver  
with 3-STATE Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT240 and LVTH240 are inverting octal buffers and  
line drivers designed to be employed as memory address  
drivers, clock drivers and bus oriented transmitters or  
receivers which provides improved PC board density.  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH240),  
also available without bushold feature (74LVT240)  
The LVTH240 data inputs include bushold, eliminating the  
need for external pull-up resistors to hold unused inputs.  
■ Live insertion/extraction permitted  
These octal buffers and line drivers are designed for low-  
voltage (3.3V) VCC applications, but with the capability to  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
provide a TTL interface to a 5V environment. The LVT240  
and LVTH240 are fabricated with an advanced BiCMOS  
technology to achieve high speed operation similar to 5V  
ABT while maintaining low power dissipation.  
■ Outputs source/sink 32 mA/ 64 mA  
■ Functionally compatible with the 74 series 240  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
Human-body model 2000V  
Machine model 200V  
Charged-device model 1000V  
Ordering Code:  
Package  
Order Number  
Package Description  
Number  
74LVT240WM  
74LVT240SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVT240MSA  
74LVT240MTC  
MSA20  
MTC20  
MTC20  
74LVT240MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
74LVTH240WM  
74LVTH240SJ  
M20B  
M20D  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
74LVTH240MSA  
74LVTH240MTC  
MSA20  
MTC20  
MTC20  
74LVTH240MTCX_NL  
(Note 1)  
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm  
Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Pb-Free package per JECED J-STD-020B.  
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.  
© 2005 Fairchild Semiconductor Corporation  
DS500153  
www.fairchildsemi.com  
12345678

中文翻译

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74LVTH240SJX 替代型号

型号 品牌 替代类型 描述 数据表
74LVTH2240SJ FAIRCHILD

类似代替

 Low Voltage Inverting Octal Buffer/Line Driver with 3-STATE Outputs
74LVT240SJ FAIRCHILD

类似代替

 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

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