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74LVTH16952MTD PDF预览

74LVTH16952MTD

更新时间: 2024-11-04 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
页数 文件大小 规格书
8页 78K
描述
Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

74LVTH16952MTD 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP, TSSOP56,.3,20
针数:56Reach Compliance Code:compliant
风险等级:5.37其他特性:WITH INDEPENDENT OUTPUT ENABLE FOR EACH DIRECTION
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:LVTJESD-30 代码:R-PDSO-G56
JESD-609代码:e4长度:14 mm
逻辑集成电路类型:REGISTERED BUS TRANSCEIVER最大I(ol):0.064 A
湿度敏感等级:2位数:8
功能数量:2端口数量:2
端子数量:56最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP56,.3,20
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:4.8 ns传播延迟(tpd):5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:6.1 mmBase Number Matches:1

74LVTH16952MTD 数据手册

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January 2000  
Revised October 2001  
74LVT16952 74LVTH16952  
Low Voltage 16-Bit Registered Transceiver  
with 3-STATE Outputs  
General Description  
Features  
Input and output interface capability to systems at  
The LVT16952 and LVTH16952 are 16-bit registered  
transceivers. Two 8-bit back to back registers store data  
flowing in both directions between two bidirectional buses.  
Separate clock, clock enable, and output enable signals  
are provided for each register.  
5V VCC  
Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16952)  
Live insertion/extraction permitted  
The LVTH16952 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
Power Up/Down high impedance provides glitch-free  
bus loading  
Outputs source/sink 32 mA/+64 mA  
Functionally compatible with the 74 series 16952  
Latch-up conforms to JEDEC JED78  
ESD performance:  
The registered transceiver is designed for low-voltage  
(3.3V) VCC applications, but with the capability to provide a  
TTL interface to a 5V environment.  
The LVT16952 and LVTH16952 are fabricated with an  
advanced BiCMOS technology to achieve high speed oper-  
ation similar to 5V ABT while maintaining low power dissi-  
pation.  
Human-body model > 2000V  
Machine model > 200V  
Charged-device model > 1000V  
Ordering Code:  
Order Number Package Number  
Package Description  
74LVT16952MEA  
(Preliminary)  
MS56A  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVT16952MTD  
(Preliminary)  
MTD56  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVTH16952MEA  
74LVTH16952MTD  
MS56A  
MTD56  
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2001 Fairchild Semiconductor Corporation  
DS500103  
www.fairchildsemi.com  

74LVTH16952MTD 替代型号

型号 品牌 替代类型 描述 数据表
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