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74LVTH16373GX PDF预览

74LVTH16373GX

更新时间： 2024-11-20 21:54:07
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器锁存器逻辑集成电路信息通信管理
页数 文件大小 规格书
8页 100K
描述
Low Voltage 16-Bit Transparent Latch with 3-STATE Outputs

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中文翻译

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74LVTH16373GX 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：LFBGA, BGA54,6X9,32
针数：54Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：5.74
系列：LVTJESD-30 代码：R-PBGA-B54
JESD-609代码：e0长度：8 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.064 A位数：8
功能数量：2端口数量：2
端子数量：54最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：LFBGA封装等效代码：BGA54,6X9,32
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 VProp。Delay @ Nom-Sup：3.9 ns
传播延迟（tpd）：4.8 ns认证状态：Not Qualified
座面最大高度：1.4 mm子类别：FF/Latches
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：BALL
端子节距：0.8 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：5.5 mm
Base Number Matches：1

74LVTH16373GX 数据手册

 浏览型号74LVTH16373GX的Datasheet PDF文件第2页浏览型号74LVTH16373GX的Datasheet PDF文件第3页浏览型号74LVTH16373GX的Datasheet PDF文件第4页浏览型号74LVTH16373GX的Datasheet PDF文件第5页浏览型号74LVTH16373GX的Datasheet PDF文件第6页浏览型号74LVTH16373GX的Datasheet PDF文件第7页 
January 1999  
Revised June 2005  
74LVT16373 • 74LVTH16373  
Low Voltage 16-Bit Transparent Latch  
with 3-STATE Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT16373 and LVTH16373 contain sixteen non-invert-  
ing latches with 3-STATE outputs and is intended for bus  
oriented applications. The device is byte controlled. The  
flip-flops appear transparent to the data when the Latch  
Enable (LE) is HIGH. When LE is LOW, the data that meets  
the setup time is latched. Data appears on the bus when  
the Output Enable (OE) is LOW. When OE is HIGH, the  
outputs are in a high impedance state.  
5V VCC  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH16373),  
also available without bushold feature (74LVT16373)  
■ Live insertion/extraction permitted  
■ Power Up/Power Down high impedance provides  
glitch-free bus loading  
The LVTH16373 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Outputs source/sink 32 mA/ 64 mA  
■ Functionally compatible with the 74 series 16373  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
These latches are designed for low-voltage (3.3V) VCC  
applications, but with the capability to provide a TTL inter-  
face to a 5V environment. The LVT16373 and LVTH16373  
are fabricated with an advanced BiCMOS technology to  
achieve high speed operation similar to 5V ABT while  
maintaining a low power dissipation.  
Human-body model 2000V  
Machine model 200V  
Charged-device model 1000V  
■ Also packaged in plastic Fine-Pitch Ball Grid Array  
(FBGA) (Preliminary)  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74LVT16373GX  
(Note 1)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[TAPE and REEL]  
74LVT16373MEA  
(Note 2)  
MS48A  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVT16373MTD  
(Note 2)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVTH16373GX  
(Note 1)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
[TAPE and REEL]  
74LVTH16373MEA  
(Note 2)  
MS48A  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVTH16373MTD  
(Note 2)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Note 1: BGA package available in Tape and Reel only.  
Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
© 2005 Fairchild Semiconductor Corporation  
DS012021  
www.fairchildsemi.com  
12345678

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