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74LVTH162240MTX_NL PDF预览

74LVTH162240MTX_NL

更新时间： 2024-09-10 20:00:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动信息通信管理光电二极管逻辑集成电路
页数 文件大小 规格书
6页 76K
描述
Bus Driver, LVT Series, 4-Func, 4-Bit, Inverted Output, BICMOS, PDSO48, 6.10 MM, MO-153ED, TSSOP-48

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74LVTH162240MTX_NL 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：TSSOP, TSSOP48,.3,20
针数：48Reach Compliance Code：compliant
风险等级：5.13控制类型：ENABLE LOW
系列：LVTJESD-30 代码：R-PDSO-G48
JESD-609代码：e3长度：12.5 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.012 A
湿度敏感等级：2位数：4
功能数量：4端口数量：2
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出特性：3-STATE WITH SERIES RESISTOR
输出极性：INVERTED封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP48,.3,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
包装方法：TAPE AND REEL峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：4 ns
传播延迟（tpd）：4.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

74LVTH162240MTX_NL 数据手册

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June 1999  
Revised June 2005  
74LVT162240 • 74LVTH162240  
Low Voltage 16-Bit Inverting Buffer/Line Driver  
with 3-STATE Outputs and  
25: Series Resistors in the Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT162240 and LVTH162240 contain sixteen inverting  
buffers with 3-STATE outputs designed to be employed as  
a memory and address driver, clock driver, or bus oriented  
transmitter/receiver. The device is nibble controlled. Indi-  
vidual 3-STATE control inputs can be shorted together for  
8-bit or 16-bit operation.  
5V VCC  
■ Outputs include equivalent series resistance of 25 to  
make external termination resistors unnecessary and  
reduce overshoot and undershoot  
■ Bushold data inputs eliminate the need for external  
pull-up resistors to hold unused inputs (74LVTH162240),  
also available without bushold feature (74LVT162240)  
The LVT162240 and LVTH162240 are designed with  
equivalent 25 series resistance in both the HIGH and  
LOW states of the output. This design reduces line noise in  
applications such as memory address drivers, clock driv-  
ers, and bus transceivers/transmitters.  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
The LVTH162240 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Functionally compatible with the 74 series 162240  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
These inverting buffers and line drivers are designed for  
low-voltage (3.3V) VCC applications, but with the capability  
Human-body model 2000V  
to provide a TTL interface to a 5V environment. The  
LVT162240 and LVTH162240 are fabricated with an  
advanced BiCMOS technology to achieve high speed oper-  
ation similar to 5V ABT while maintaining a low power dis-  
sipation.  
Machine model 200V  
Charged-device model 1000V  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74LVT162240MEA  
(Note 1)  
MS48A  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
74LVT162240MTD  
(Note 1)  
MTD48  
MS48A  
MS48A  
MTD48  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
74LVTH162240MEA  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
[TUBE]  
74LVTH162240MEX  
(Note 2)  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
[TAPE and REEL]  
74LVTH162240MTD  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
[TUBE]  
74LVTH162240MTX  
(Note 2)  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
[TAPE and REEL]  
Note 1: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Note 2: Use this Order Number to receive devices in Tape and Reel.  
© 2005 Fairchild Semiconductor Corporation  
DS012490  
www.fairchildsemi.com  
123456

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