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74LVTH162240MTD PDF预览

74LVTH162240MTD

更新时间： 2024-09-09 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
6页 56K
描述
Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25ヘ Series Resistors in the Outputs

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中文翻译

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74LVTH162240MTD 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, MO-153ED, TSSOP-48
针数：48Reach Compliance Code：unknown
风险等级：5.11Is Samacsys：N
控制类型：ENABLE LOW系列：LVT
JESD-30 代码：R-PDSO-G48JESD-609代码：e3
长度：12.5 mm逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.012 A湿度敏感等级：2
位数：4功能数量：4
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 VProp。Delay @ Nom-Sup：4 ns
传播延迟（tpd）：4.8 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：BICMOS温度等级：INDUSTRIAL
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.1 mm
Base Number Matches：1

74LVTH162240MTD 数据手册

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June 1999  
Revised June 1999  
74LVT162240 • 74LVTH162240  
Low Voltage 16-Bit Inverting Buffer/Line Driver  
with 3-STATE Outputs and  
25Ω Series Resistors in the Outputs  
advanced BiCMOS technology to achieve high speed oper-  
ation similar to 5V ABT while maintaining a low power dis-  
sipation.  
General Description  
The LVT162240 and LVTH162240 contain sixteen inverting  
buffers with 3-STATE outputs designed to be employed as  
a memory and address driver, clock driver, or bus oriented  
transmitter/receiver. The device is nibble controlled. Indi-  
vidual 3-STATE control inputs can be shorted together for  
8-bit or 16-bit operation.  
Features  
■ Input and output interface capability to systems at  
5V VCC  
The LVT162240 and LVTH162240 are designed with  
equivalent 25Ω series resistance in both the HIGH and  
LOW states of the output. This design reduces line noise in  
applications such as memory address drivers, clock driv-  
ers, and bus transceivers/transmitters.  
■ Outputs include equivalent series resistance of 25Ω to  
make external termination resistors unnecessary and  
reduce overshoot and undershoot  
■ Bushold data inputs eliminate the need for external pull-  
up resistors to hold unused inputs (74LVTH162240),  
also available without bushold feature (74LVT162240).  
The LVTH162240 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
These inverting buffers and line drivers are designed for  
low-voltage (3.3V) VCC applications, but with the capability  
■ Functionally compatible with the 74 series 162240  
■ Latch-up performance exceeds 500 mA  
to provide a TTL interface to a 5V environment. The  
LVT162240 and LVTH162240 are fabricated with an  
Ordering Code:  
Order Number  
74LVT162240MEA  
74LVT162240MTD  
74LVTH162240MEA  
74LVTH162240MTD  
Package Number  
MS48A  
Package Description  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300” Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
MTD48  
MS48A  
MTD48  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
Output Enable Inputs (Active LOW)  
Inputs  
I0–I15  
O0–O15  
3-STATE Outputs  
© 1999 Fairchild Semiconductor Corporation  
DS012490  
www.fairchildsemi.com  
123456

中文翻译

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74LVTH162240MTD 替代型号

型号 品牌 替代类型 描述 数据表
CLVTH162240IDGGREP TI

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